公开(公告)号：US20240407170A1

公开(公告)日：2024-12-05

申请号：US18659256

申请日：2024-05-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Raman Gaire ,  Hsueh Chung Chen ,  In Soo Jung ,  Houssam Lazkani ,  Hui Zhao ,  Liu Jiang ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi

IPC: H10B43/40 ,  H10B41/35 ,  H10B41/49 ,  H10B43/23 ,  H10B43/35

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

公开(公告)号：US20240290883A1

公开(公告)日：2024-08-29

申请号：US18441808

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Hui Zhao ,  Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.

公开(公告)号：US20240234544A1

公开(公告)日：2024-07-11

申请号：US18538267

申请日：2023-12-13

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Liu Jiang ,  El Mehdi Bazizi ,  Byeong Chan Lee ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  C23C16/02 ,  C23C16/04 ,  C23C16/32 ,  C23C16/40 ,  C23C16/56 ,  C30B25/04 ,  C30B25/18 ,  C30B29/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66553 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/325 ,  C23C16/401 ,  C23C16/56 ,  C30B25/04 ,  C30B25/186 ,  C30B29/06 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

公开(公告)号：US20240120193A1

公开(公告)日：2024-04-11

申请号：US17960569

申请日：2022-10-05

Applicant: Applied Materials, Inc.

Inventor： Shankar Venkataraman ,  Zeqing Shen ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Lakmal C. Kalutarage ,  Jongbeom Seo ,  Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/02126 ,  H01L21/0206 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/31116 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/42392

Abstract: Exemplary methods of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting a remaining silicon-containing material with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the silicon-containing material. The methods may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the cleaning agent. The contacting with the cleaning precursor may remove surface oxide from the substrate.

公开(公告)号：US20230061392A1

公开(公告)日：2023-03-02

申请号：US17897372

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

公开(公告)号：US20250112054A1

公开(公告)日：2025-04-03

申请号：US18894665

申请日：2024-09-24

Applicant: Applied Materials, Inc.

Inventor： Yuriy Shusterman ,  Sean Reidy ,  Sai Hooi Yeong ,  Lisa Megan McGill ,  Benjamin Colombeau ,  Andre P. Labonte ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/26 ,  H01L21/311

Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

公开(公告)号：US20240365551A1

公开(公告)日：2024-10-31

申请号：US18630142

申请日：2024-04-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Steven C. H. Hung ,  Hsueh Chung Chen ,  Naomi Yoshida ,  Sung-Kwan Kang ,  Balasubramanian Pranatharthiharan

IPC: H10B43/35 ,  H01L21/67 ,  H01L23/528 ,  H01L23/532 ,  H10B43/20

CPC classification number: H10B43/35 ,  H01L21/67161 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H10B43/20

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

公开(公告)号：US20230260909A1

公开(公告)日：2023-08-17

申请号：US18106643

申请日：2023-02-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Yeoh ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Ashish Pal

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/401 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.

公开(公告)号：US20230260908A1

公开(公告)日：2023-08-17

申请号：US18106621

申请日：2023-02-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Yeoh ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Ashish Pal ,  El Mehdi Bazizi

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/66553 ,  H01L29/66439

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

公开(公告)号：US20230164993A1

公开(公告)日：2023-05-25

申请号：US18055058

申请日：2022-11-14

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Balasubramanian Pranatharthiharan ,  Mukund Srinivasan

IPC: H01L27/11578 ,  G11C5/06 ,  H01L27/1157

CPC classification number: H01L27/11578 ,  G11C5/063 ,  H01L27/1157

Abstract: Described is a memory device including a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate. Each of the plurality of memory cells comprises a discrete blocking oxide layer, a charge trap layer, and a tunnel oxide layer. The blocking oxide layer is discrete between each of the plurality of memory cells. The tunnel oxide layer is continuous between each of the plurality of memory cells, and the charge trap layer is discrete between each of the plurality of memory cells. The charge trap layer has a first thickness on a top portion and a second thickness on a center portion, the first thickness different than the second thickness.