公开(公告)号：US20170170136A1

公开(公告)日：2017-06-15

申请号：US15236814

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Seung-kwan RYU ,  Cha-jea JO ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US20170047310A1

公开(公告)日：2017-02-16

申请号：US15183778

申请日：2016-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Bo SHIM ,  Seung-Duk BAEK ,  Cha-Jea JO ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate, a semiconductor chip and a molding member. A protrusion may be formed on a side surface of the package substrate. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the package substrate. The molding member may be formed on the upper surface and the side surface of the package substrate, and an upper surface of the protrusion. Thus, the molding member on the protrusion of the package substrate may be configured to cover the side surface of the package substrate so that the side surface of the package substrate may not be exposed.

Abstract translation: 半导体封装可以包括封装衬底，半导体芯片和模制构件。 突起可以形成在封装基板的侧表面上。 半导体芯片可以布置在封装衬底的上表面上。 半导体芯片可以与封装衬底电连接。 成型构件可以形成在封装基板的上表面和侧表面以及突起的上表面上。 因此，封装基板的突起部上的成型部件可以构成为覆盖封装基板的侧面，使得封装基板的侧面不会露出。

公开(公告)号：US20170229412A1

公开(公告)日：2017-08-10

申请号：US15494942

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Seung-kwan RYU ,  Cha-jea JO ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/14519 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US20170047309A1

公开(公告)日：2017-02-16

申请号：US15158921

申请日：2016-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Duk BAEK ,  Jong-Bo SHIM ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3171 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: A fabricating method of a semiconductor device, in which a first semiconductor chip having a desired first thickness and a semiconductor chip having a desired second thickness are used to fabricate a semiconductor device having a desired third thickness that is greater than the sum of the first and second thicknesses includes providing the first semiconductor chip, which has the first thickness, forming the second semiconductor chip, which is connected to the first semiconductor chip via through silicon vias (TSVs) and has the second thickness, on the first semiconductor chip, and providing a dummy semiconductor chip, which is not electrically connected to the semiconductor chip and has a fourth thickness, on the second semiconductor chip, wherein the fourth thickness is generated based on a difference between about the third thickness and about a sum of the first and second thicknesses.

Abstract translation: 一种半导体器件的制造方法，其中使用具有期望的第一厚度的第一半导体芯片和具有期望的第二厚度的半导体芯片来制造具有期望的第三厚度的半导体器件，所述第三厚度大于第一和第二厚度之和的半导体器件， 第二厚度包括提供具有第一厚度的第一半导体芯片，形成第二半导体芯片，第二半导体芯片经由第一半导体芯片上的硅通孔（TSV）连接到第一半导体芯片并具有第二厚度，并且提供 在所述第二半导体芯片上未与所述半导体芯片电连接并具有第四厚度的虚设半导体芯片，其中所述第四厚度基于所述第三厚度和所述第一和第二厚度之和之间的差大小而产生 厚度

公开(公告)号：US20160093518A1

公开(公告)日：2016-03-31

申请号：US14788783

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Dong JUNG ,  Jung-Hwan KIM ,  Dong-Gil LEE ,  Tae-Je CHO ,  Kwang-Chul CHOI

IPC: H01L21/67 ,  B32B43/00

CPC classification number: H01L21/67115 ,  B32B38/10 ,  B32B41/00 ,  B32B43/006 ,  B32B2250/02 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L21/67092 ,  H01L21/67253 ,  H01L2221/68381 ,  H01L2224/98 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

Abstract translation: 提供了一种用于剥离晶片支撑系统的引发剂和方法。 用于剥离晶片支撑系统的启动器包括具有上表面的旋转卡盘，其上包括载体晶片的晶片支撑系统（WSS），器件晶片和用于将载体晶片和器件晶片接合的胶层 彼此坐下来旋转晶片支撑系统，检测模块检测胶层的高度和厚度;以及激光模块，其通过用激光照射胶层的侧表面而在胶层上产生断裂部分 胶层的高度和厚度的基础。

公开(公告)号：US20150228591A1

公开(公告)日：2015-08-13

申请号：US14559446

申请日：2014-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang KIM ,  Keum-Hee MA ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/367 ,  H01L23/522

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81801 ,  H01L2224/81986 ,  H01L2224/9202 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor package including a chip stack structure having first and second chips that are secured to a dissipating plate by using a mold layer such that the second chip is combined to the dissipating plate and the first chip is bonded to the second chip, and the first chip has a smaller thickness than the second chip, a circuit board onto which the chip stack structure is mounted in a bonded manner, and an under-fill layer filling a gap space between the circuit board and first chip, a side surface of the under-fill layer being connected to a sidewall of the mold layer may be provided. Due to this bulk mounting structure, the warpage and bonding failures of the semiconductor package may be substantially reduced.

Abstract translation: 一种半导体封装，包括具有第一和第二芯片的芯片堆叠结构，所述芯片堆叠结构通过使用模具层固定到散热板，使得所述第二芯片组合到所述散热板并且所述第一芯片被结合到所述第二芯片，并且所述第一芯片 芯片具有比第二芯片小的厚度，以键合方式安装芯片堆叠结构的电路板，以及填充电路板和第一芯片之间的间隙空间的欠填充层，底部的侧表面 可以提供连接到模具层的侧壁的填充层。 由于该散装安装结构，可以显着地减少半导体封装的翘曲和接合故障。

公开(公告)号：US20150137345A1

公开(公告)日：2015-05-21

申请号：US14504309

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung CHOI ,  Sang-Uk HAN ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L23/04 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49816 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability.

Abstract translation: 半导体封装包括散热器。 半导体封装包括衬底，设置在衬底上的第一半导体芯片和设置在第一半导体芯片上的第二半导体芯片。 散热器可以形成在第一半导体芯片上。 热界面材料（TIM）层可以形成为与第一半导体芯片和散热器接触并且可以覆盖第二半导体芯片的侧表面。 可以通过TIM层和散热器发射由第一半导体芯片产生的热量。 可以分配由基板和第一半导体芯片之间的热膨胀系数（CTE）引起的热应力，以确保结构稳定性。

公开(公告)号：US20150130083A1

公开(公告)日：2015-05-14

申请号：US14488707

申请日：2014-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick PARK ,  In-Young LEE ,  Byoung-Soo KWAK ,  Min-Soo KIM ,  Sang-Wook PARK ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L23/34 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Abstract translation: 一种半导体器件及其制造方法包括提供具有第一连接端子的第一半导体芯片，提供第二半导体芯片，该第二半导体芯片包括彼此相对的顶表面和底表面，并且具有第二连接端子和形成的膜型第一底部填充材料 在其底面上，通过使用第一连接端子将第一半导体芯片接合到安装基板，通过使用第一底部填充材料接合第一半导体芯片和第二半导体芯片，以及形成填充第二底部填充材料之间的空间的第二底部填充材料 安装基板和第一半导体芯片，并且覆盖第一半导体芯片的侧表面和第二半导体芯片的至少一部分侧表面。

公开(公告)号：US20140147974A1

公开(公告)日：2014-05-29

申请号：US14171048

申请日：2014-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Hyeok IM ,  Jong-Yeon KIM ,  Tae-Je CHO ,  Un-Byoung KANG

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/13025 ,  H01L2224/13075 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.

Abstract translation: 提供一种凸块结构，包括第一凸块和第二凸块，包括该凸块的半导体封装及其制造方法。 凸块结构包括：设置在基板的连接焊盘上的第一凸块，所述第一凸块包括从所述连接焊盘延伸的多个纳米线和连接所述多个纳米线的端部的主体; 以及设置在第一凸块的主体上的第二凸块。

公开(公告)号：US20140057430A1

公开(公告)日：2014-02-27

申请号：US14072777

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin LEE ,  Tae-Je CHO ,  Dong-Hyeon JANG ,  Ho-Geon SONG ,  Se-Young JEONG ,  Un-Byoung KANG ,  Min-Seung YOON

IPC: H01L21/768

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract translation: 在一个实施例中，半导体器件包括具有第一表面的半导体衬底和与第一表面相对的第二表面。 第二表面限定再分布沟槽。 基板具有贯穿其中的通孔。 半导体器件还包括设置在通孔中的贯通孔。 通孔可以包括依次形成在通孔的内壁上的通孔绝缘层，阻挡层。 通孔还可以包括邻近阻挡层的导电连接器。 半导体器件还包括形成在衬底的第二表面上的绝缘层图案。 绝缘层图案限定了暴露通孔的顶表面的区域的开口。 半导体器件包括设置在沟槽中并与通孔电连接的再分配层。 绝缘层图案与导电连接器的区域重叠。