公开(公告)号：US20230361219A1

公开(公告)日：2023-11-09

申请号：US18136431

申请日：2023-04-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Mitsuhiro ICHIJO ,  Toshiya ENDO ,  Akihisa SHIMOMURA ,  Yuji EGI ,  Sachiaki TEZUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78606 ,  H01L29/78648

Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.

公开(公告)号：US20180151750A1

公开(公告)日：2018-05-31

申请号：US15879023

申请日：2018-01-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hideomi SUZAWA ,  Tetsuhiro TANAKA ,  Yuhei SATO ,  Sachiaki TEZUKA ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/78648 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/41733 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A transistor having high field-effect mobility is provided. A transistor having stable electrical characteristics is provided. A transistor having small current in an off state (in a non-conductive state) is provided. A semiconductor device including such a transistor is provided. A first electrode is formed over a substrate, a first insulating layer is formed adjacent to a side surface of the first electrode, and a second insulating layer is formed to cover the first insulating layer and be in contact with at least part of a surface of the first electrode. The surface of the first electrode is formed of a conductive material that does not easily transmit an impurity element. The second insulating layer is formed of an insulating material that does not easily transmit an impurity element. An oxide semiconductor layer is formed over the first electrode with a third insulating layer provided therebetween.

公开(公告)号：US20180047753A1

公开(公告)日：2018-02-15

申请号：US15723227

申请日：2017-10-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Tetsuhiro TANAKA ,  Yoshinori IEDA ,  Toshiyuki MIYAMOTO ,  Masafumi NOMURA ,  Takashi HAMOCHI ,  Kenichi OKAZAKI ,  Mitsuhiro ICHIJO ,  Toshiya ENDO

IPC: H01L27/12 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L27/1207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1225

Abstract: A nitride insulating film which prevents diffusion of hydrogen into an oxide semiconductor film in a transistor including an oxide semiconductor is provided. Further, a semiconductor device which has favorable electrical characteristics by using a transistor including a silicon semiconductor and a transistor including an oxide semiconductor is provided. Two nitride insulating films having different functions are provided between the transistor including a silicon semiconductor and the transistor including an oxide semiconductor. Specifically, a first nitride insulating film which contains hydrogen is provided over the transistor including a silicon semiconductor, and a second nitride insulating film which has a lower hydrogen content than the first nitride insulating film and functions as a barrier film against hydrogen is provided between the first nitride insulating film and the transistor including an oxide semiconductor.

公开(公告)号：US20170018631A1

公开(公告)日：2017-01-19

申请号：US15276993

申请日：2016-09-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Akihisa SHIMOMURA ,  Yasumasa YAMANE ,  Yuhei SATO ,  Tetsuhiro TANAKA ,  Masashi TSUBUKU ,  Toshihiko TAKEUCHI ,  Ryo TOKUMARU ,  Mitsuhiro ICHIJO ,  Satoshi TORIUMI ,  Takashi OHTSUKI ,  Toshiya ENDO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film. In the antioxidant film, a width of a region overlapping with the pair of electrodes is longer than a width of a region not overlapping with the pair of electrodes.

Abstract translation: 抑制了电特性的变化，并且提高了使用包括氧化物半导体的晶体管的半导体器件的可靠性。 半导体器件包括绝缘表面上的氧化物半导体膜，绝缘表面上的抗氧化膜和氧化物半导体膜，与抗氧化膜接触的一对电极，一对电极上的栅极绝缘膜，以及栅极 电极，其在栅极绝缘膜上方并与氧化物半导体膜重叠。 在抗氧化剂膜中，与该对电极重叠的区域的宽度比不与该对电极重叠的区域的宽度长。

公开(公告)号：US20160343870A1

公开(公告)日：2016-11-24

申请号：US15230732

申请日：2016-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshitaka YAMAMOTO ,  Tetsuhiro TANAKA ,  Takayuki INOUE ,  Hideomi SUZAWA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/792 ,  H01L21/441 ,  H01L29/51 ,  H01L29/49 ,  H01L21/465 ,  H01L21/02 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02181 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31645 ,  H01L21/32136 ,  H01L21/441 ,  H01L21/465 ,  H01L21/473 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/40117 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696 ,  H01L29/792

Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P≧45−0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.

公开(公告)号：US20160163744A1

公开(公告)日：2016-06-09

申请号：US15041338

申请日：2016-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Tetsuhiro TANAKA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02609 ,  H01L21/02617 ,  H01L21/02631 ,  H01L29/045 ,  H01L29/26 ,  H01L29/78 ,  H01L29/7869

Abstract: A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. A semiconductor device includes an oxide semiconductor layer in a channel formation region, and by the use of an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer, oxygen of the oxide insulating film or the gate insulating film is supplied to the oxide semiconductor layer. Further, a conductive nitride is used for metal films of a source electrode layer, a drain electrode layer, and a gate electrode layer, whereby diffusion of oxygen to the metal films is suppressed.

Abstract translation: 提供了可以抑制氧化物半导体层中氧空位增加的半导体器件。 提供了具有良好电气特性的半导体器件。 提供了一种高度可靠的半导体器件。 半导体器件包括在沟道形成区域中的氧化物半导体层，并且通过使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触的栅绝缘膜， 氧化物绝缘膜或栅极绝缘膜被提供给氧化物半导体层。 此外，导电氮化物用于源电极层，漏电极层和栅电极层的金属膜，由此抑制氧向金属膜的扩散。

公开(公告)号：US20160149045A1

公开(公告)日：2016-05-26

申请号：US14941930

申请日：2015-11-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Daisuke MATSUBAYASHI ,  Kazuki TANEMURA

IPC: H01L29/786 ,  H01L29/788

CPC classification number: H01L29/7869 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/14612 ,  H01L29/1083 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696 ,  H01L29/788 ,  H01L29/7881

Abstract: A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.

Abstract translation: 半导体器件包括第一导体，第二导​​体，第一绝缘体，第二绝缘体，第三绝缘体，半导体和电子陷阱层。 半导体包括沟道形成区域。 电子捕获层与通道形成区域重叠，其间插入第二绝缘体。 第一导体与沟道形成区重叠，其间插入第一绝缘体。 第二导体与电子陷阱层重叠，其间插入第三绝缘体。 第二导体不与沟道形成区重叠。

公开(公告)号：US20160111590A1

公开(公告)日：2016-04-21

申请号：US14978463

申请日：2015-12-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Erika KATO

IPC: H01L31/20 ,  H01L31/105

CPC classification number: H01L31/20 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02592 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78648 ,  H01L29/78696 ,  H01L31/0304 ,  H01L31/03685 ,  H01L31/03687 ,  H01L31/0376 ,  H01L31/03762 ,  H01L31/03765 ,  H01L31/072 ,  H01L31/0735 ,  H01L31/105 ,  H01L31/1136 ,  H01L31/1808 ,  H01L31/1812 ,  H01L31/1816 ,  H01L31/1824 ,  H01L31/1852 ,  H01L31/202 ,  Y02E10/544 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

Abstract translation: 提供了一种用于形成含有杂质元素并具有低电阻率的非晶半导体的方法，以及制造具有优异的电特性，高产率的半导体器件的方法。 在利用等离子体CVD法形成含有杂质元素的非晶半导体的方法中，在可以获得根据帕邢定律的最小放电起始电压的压力和电极距离处的电极上施加脉冲调制放电初始电压 由此形成含有杂质元素并具有低电阻率的非晶半导体。

公开(公告)号：US20160111546A1

公开(公告)日：2016-04-21

申请号：US14883732

申请日：2015-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Hideomi SUZAWA ,  Suguru HONDO

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78

Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Abstract translation: 为包括氧化物半导体的小型半导体器件提供稳定的电特性和高可靠性，并且制造半导体器件。 半导体器件包括基极绝缘层; 氧化物堆叠，其在所述基底绝缘层上方并且包括氧化物半导体层; 氧化层上的源电极层和漏电极层; 氧化层上的栅极绝缘层，源电极层和漏电极层; 栅绝缘层上的栅电极层; 以及在栅电极层上的层间绝缘层。 在半导体器件中，氧化物半导体层中的缺陷密度降低。

公开(公告)号：US20160111545A1

公开(公告)日：2016-04-21

申请号：US14878121

申请日：2015-10-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Kazuki TANEMURA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/24 ,  H01L29/51

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes a first conductor, a second conductor, a first semiconductor, a second semiconductor, a third semiconductor, and an insulator. The second semiconductor is in contact with an upper surface of the first semiconductor. The first conductor overlaps with the second semiconductor. The insulator is located between the first conductor and the first semiconductor. The second conductor is in contact with an upper surface of the second semiconductor. The third semiconductor is in contact with the upper surface of the first semiconductor, the upper surface of the second semiconductor, and an upper surface of the second conductor.

Abstract translation: 半导体器件包括第一导体，第二导​​体，第一半导体，第二半导体，第三半导体和绝缘体。 第二半导体与第一半导体的上表面接触。 第一导体与第二半导体重叠。 绝缘体位于第一导体和第一半导体之间。 第二导体与第二半导体的上表面接触。 第三半导体与第一半导体的上表面，第二半导体的上表面和第二导体的上表面接触。