公开(公告)号：US20060172565A1

公开(公告)日：2006-08-03

申请号：US10906111

申请日：2005-02-03

申请人： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

发明人： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

IPC分类号： H01R12/00

CPC分类号： H01L24/13 ,  G01R1/06716 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L2221/68377 ,  H01L2224/11003 ,  H01L2224/114 ,  H01L2224/11505 ,  H01L2224/116 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/06 ,  H05K3/3436 ,  H05K2201/10242 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

摘要翻译： 形成顺应性电触头的方法包括将导电层图案化为顺应构件阵列。 然后将顺应构件阵列定位成与集成电路晶片上的电连接焊盘接触，并且柔性构件连接到焊盘。 然后，移除支撑柔顺构件的支撑层，以使与柔性构件连接的衬垫离开。

公开(公告)号：US20080009101A1

公开(公告)日：2008-01-10

申请号：US11858147

申请日：2007-09-20

申请人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

发明人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

摘要翻译： 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20080000080A1

公开(公告)日：2008-01-03

申请号：US11856084

申请日：2007-09-17

申请人： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

发明人： William Bernier ,  David Eichstadt ,  Mukta Farooq ,  John Knickerbocker

IPC分类号： H05K3/00

CPC分类号： H01L24/13 ,  G01R1/06716 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/81 ,  H01L2221/68377 ,  H01L2224/11003 ,  H01L2224/114 ,  H01L2224/11505 ,  H01L2224/116 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/06 ,  H05K3/3436 ,  H05K2201/10242 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method of forming compliant electrical contacts includes patterning a conductive layer into an array of compliant members. The array of compliant members is then positioned to be in contact with electrical connection pads on an integrated circuit wafer and the compliant members are joined to the pads. Then, the supporting layer that supported the compliant members is removed to leave the compliant members connected to the pads.

摘要翻译： 形成顺应性电触头的方法包括将导电层图案化为顺应构件阵列。 然后将顺应构件阵列定位成与集成电路晶片上的电连接焊盘接触，并且柔性构件连接到焊盘。 然后，移除支撑柔顺构件的支撑层，以使与柔性构件连接的衬垫离开。

公开(公告)号：US20060040567A1

公开(公告)日：2006-02-23

申请号：US10711076

申请日：2004-08-20

申请人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

发明人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

IPC分类号： H05K1/00 ,  H01R12/00 ,  H01R13/42

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

摘要翻译： 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20060009022A1

公开(公告)日：2006-01-12

申请号：US11162468

申请日：2005-09-12

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US20050245070A1

公开(公告)日：2005-11-03

申请号：US10709321

申请日：2004-04-28

申请人： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

发明人： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

IPC分类号： H01L21/288 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/00014

摘要： A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

摘要翻译： 公开了一种创建用于互连中的多层屏障的方法，用于互连的屏障和包括屏障的互连的方法。 该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。 屏障包括至少第一层富镍材料和第二层富铜材料。 阻挡层可以为高级互补金属氧化物半导体（CMOS）设计使用更高的电流密度，并扩展电流CMOS设计的可靠性，无论焊料选择如何。 而且，该技术很容易适用于电镀互连如C4的制造方法。

公开(公告)号：US20050026450A1

公开(公告)日：2005-02-03

申请号：US10604560

申请日：2003-07-30

申请人： Emanuel Cooper ,  John Cotte ,  Lisa Fanti ,  David Eichstadt ,  Stephen Kilpatrick ,  Henry Nye ,  Donna Zupanski-Nielsen

发明人： Emanuel Cooper ,  John Cotte ,  Lisa Fanti ,  David Eichstadt ,  Stephen Kilpatrick ,  Henry Nye ,  Donna Zupanski-Nielsen

IPC分类号： H01L21/302 ,  H01L21/44 ,  H01L21/461 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method is provided for removing exposed seed layers in the fabrication of solder interconnects on electronic components such as semiconductor wafers without damaging the interconnects or underlying wafer substrate and with a high wafer yield. The solder interconnects are lead free or substantially lead free and typically contain Sn. An oxalic acid solution is used to contact the wafer after an etching step to remove part of the seed layer. The seed layer is typically a Cu containing layer with a lower barrier layer containing barrier metals such as Ti, Ta and W. The lower barrier layer remains after the etch and the oxalic acid solution inhibits the formation of Sn compounds on the barrier layer surface which compounds may mask the barrier layer and the barrier layer etchant resulting in incomplete barrier layer removal on the wafer surface. Any residual conductive barrier layer can cause shorts and other wafer problems and result in a lower wafer yield. An electroetch is preferred to remove the portion of the seed layer overlying the lower barrier layer.

摘要翻译： 提供了一种在电子部件如半导体晶片制造焊料互连件中去除暴露的种子层的方法，而不会损坏互连或下面的晶片衬底并以高的晶片产量。 焊料互连是无铅的或基本上无铅的，并且通常含有Sn。 在蚀刻步骤之后，使用草酸溶液接触晶片以除去部分种子层。 种子层通常是含Cu层，其具有包含阻挡金属如Ti，Ta和W的下阻挡层。在蚀刻后保留下阻挡层，并且草酸溶液抑制在阻挡层表面上形成Sn化合物 化合物可以掩蔽阻挡层和阻挡层蚀刻剂，导致晶片表面上不完全的阻挡层去除。 任何残留的导电阻挡层可能导致短路和其他晶片问题，并导致较低的晶圆产量。 优选去除电子蚀刻以去除覆盖在下阻挡层上的种子层的部分。

公开(公告)号：US20060249854A1

公开(公告)日：2006-11-09

申请号：US11478933

申请日：2006-06-29

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。

公开(公告)号：US20050208748A1

公开(公告)日：2005-09-22

申请号：US10708649

申请日：2004-03-17

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/48 ,  H01L23/485

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US20050062170A1

公开(公告)日：2005-03-24

申请号：US10666775

申请日：2003-09-18

申请人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

发明人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，该导电焊盘与覆盖该焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。