公开(公告)号：US20060040567A1

公开(公告)日：2006-02-23

申请号：US10711076

申请日：2004-08-20

申请人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

发明人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

IPC分类号： H05K1/00 ,  H01R12/00 ,  H01R13/42

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

摘要翻译： 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20080009101A1

公开(公告)日：2008-01-10

申请号：US11858147

申请日：2007-09-20

申请人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

发明人： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

摘要： Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

摘要翻译： 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20050167837A1

公开(公告)日：2005-08-04

申请号：US10707892

申请日：2004-01-21

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/485 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。

公开(公告)号：US20050104208A1

公开(公告)日：2005-05-19

申请号：US10707021

申请日：2003-11-14

申请人： James Bartelo ,  Tien-Jen Cheng ,  David Eichstadt ,  Charles Goldsmith ,  Jonathan Griffith ,  Donald Henderson ,  Roger Quon ,  Stephen Kilpatrick

发明人： James Bartelo ,  Tien-Jen Cheng ,  David Eichstadt ,  Charles Goldsmith ,  Jonathan Griffith ,  Donald Henderson ,  Roger Quon ,  Stephen Kilpatrick

IPC分类号： H01L23/485 ,  H01L23/48

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： Disclosed is an improved integrated circuit structure that has internal circuitry and interconnects (e.g. C4, etc.) on an external portion of the structure. With the invention, these interconnects have a metal layer on the external portion of the structure, a first copper layer on the metal layer, a barrier layer on the copper layer, a stabilizing copper layer on the barrier layer, and a tin-based solder bump on the barrier layer. The stabilizing copper layer has a sufficient amount of copper to balance the chemical potential gradient of copper across the barrier layer and prevent copper within the first copper layer from diffusing across the barrier layer. Alternatively, a sufficient amount of copper can be included within the tin-based solder bump to prevent copper from diffusing across the barrier layer. Thus, the tin-based solder bump comprises a copper rich solder alloy.

摘要翻译： 公开了一种改进的集成电路结构，其在该结构的外部部分上具有内部电路和互连（例如C4等）。 通过本发明，这些互连在结构的外部具有金属层，金属层上的第一铜层，铜层上的阻挡层，阻挡层上的稳定铜层和锡基焊料 在阻挡层上碰撞。 稳定铜层具有足够量的铜以平衡横跨阻挡层的铜的化学势梯度，并防止第一铜层内的铜扩散穿过势垒层。 或者，可以在锡基焊料凸块内包含足够量的铜，以防止铜在阻挡层上扩散。 因此，锡基焊料凸块包括富含铜的焊料合金。

公开(公告)号：US20050026416A1

公开(公告)日：2005-02-03

申请号：US10604578

申请日：2003-07-31

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Kevin Petrarca ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Kevin Petrarca ,  Roger Quon

IPC分类号： H01L21/60 ,  H01L21/44 ,  H01L23/48 ,  H05K3/34 ,  H05K3/40

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K3/3457 ,  H05K3/4007 ,  H01L2224/05099

摘要： A solder bump for bonding an electronic device to a substrate or another structure is formed by plating a high aspect ratio copper pin on a supporting structure, encapsulating the pin in a barrier material, plating a solder on the barrier material and then reflowing the solder.

摘要翻译： 通过在支撑结构上镀覆高纵横比的铜针，将该引脚封装在阻挡材料中，将焊料电镀在阻挡材料上，然后回流焊料，形成用于将电子器件接合到衬底或其它结构的焊料凸块。

公开(公告)号：US20060009022A1

公开(公告)日：2006-01-12

申请号：US11162468

申请日：2005-09-12

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US20050245070A1

公开(公告)日：2005-11-03

申请号：US10709321

申请日：2004-04-28

申请人： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

发明人： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

IPC分类号： H01L21/288 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/00014

摘要： A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

摘要翻译： 公开了一种创建用于互连中的多层屏障的方法，用于互连的屏障和包括屏障的互连的方法。 该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。 屏障包括至少第一层富镍材料和第二层富铜材料。 阻挡层可以为高级互补金属氧化物半导体（CMOS）设计使用更高的电流密度，并扩展电流CMOS设计的可靠性，无论焊料选择如何。 而且，该技术很容易适用于电镀互连如C4的制造方法。

公开(公告)号：US20060081981A1

公开(公告)日：2006-04-20

申请号：US11271760

申请日：2005-11-10

申请人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

发明人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

公开(公告)号：US20050103636A1

公开(公告)日：2005-05-19

申请号：US10707047

申请日：2003-11-18

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Rosemary Previti-Kelly ,  Roger Quon ,  Kamalesh Srivastava ,  Keith Wong

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Rosemary Previti-Kelly ,  Roger Quon ,  Kamalesh Srivastava ,  Keith Wong

IPC分类号： C25D5/00 ,  C25D5/02 ,  C25D5/12 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L24/13 ,  C25D5/022 ,  C25D5/12 ,  C25D7/123 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/29099 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.

摘要翻译： 一种用于半导体输入/输出（I / O）焊盘的选择性电镀的方法包括在半导体衬底上的钝化层上形成钛 - 钨（TiW）层，所述TiW层进一步延伸到形成在钝化层中的开口中 暴露I / O焊盘，使得TiW层覆盖开口的侧壁和I / O焊盘的顶表面。 在TiW层上形成种子层，并且选择性地去除种子层的部分，使得剩余的种子层材料对应于用于I / O焊盘的互连冶金的期望位置。 使用TiW层作为导电电镀介质，在剩余的种子层材料上电镀至少一层金属层。

公开(公告)号：US20060249854A1

公开(公告)日：2006-11-09

申请号：US11478933

申请日：2006-06-29

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。