公开(公告)号：US20180054889A1

公开(公告)日：2018-02-22

申请号：US15603326

申请日：2017-05-23

Applicant: Sierra Circuits, Inc.

Inventor： Kenneth S. BAHL ,  Konstantine KARAVAKIS

IPC: H05K1/03 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K1/11 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02

CPC classification number: H05K1/0313 ,  H05K1/0296 ,  H05K1/0353 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/038 ,  H05K1/09 ,  H05K1/115 ,  H05K3/18 ,  H05K3/181 ,  H05K3/182 ,  H05K3/387 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4632 ,  H05K2201/0209 ,  H05K2201/0227 ,  H05K2201/0242 ,  H05K2201/0376 ,  H05K2203/0716

Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.

公开(公告)号：US20160135297A1

公开(公告)日：2016-05-12

申请号：US15001140

申请日：2016-01-19

Applicant: SIERRA CIRCUITS, INC.

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/09 ,  H05K3/00

CPC classification number: H05K3/387 ,  H05K3/427 ,  H05K2201/0221 ,  H05K2201/0236 ,  H05K2203/0709 ,  Y10T29/49167

Abstract: A via in a printed circuit board is composed of a patterned metal layer that extends through a hole in dielectric laminate material. A layer of catalytic adhesive coats walls within the hole. The patterned metal layer is placed over the catalytic adhesive within the hole.

Abstract translation: 印刷电路板中的通孔由延伸穿过介电层压材料中的孔的图案化金属层组成。 一层催化粘合剂涂在孔内的墙壁。 图案化金属层放置在孔内的催化粘合剂上。

公开(公告)号：US20150329971A1

公开(公告)日：2015-11-19

申请号：US14652127

申请日：2013-11-01

Applicant: KOREA INSTITUTE OF INDUSTERIAL TECHNOLOGY

Inventor： Hong-Kee LEE ,  Ho-Nyun LEE ,  Jin-Young HUR ,  Jang-Hun LEE ,  Yoon-Sung HAN

IPC: C23C18/16 ,  C23C14/22 ,  C23C28/02 ,  C25D3/38 ,  C25D5/54 ,  C25D5/34

CPC classification number: C23C18/165 ,  C23C14/16 ,  C23C14/22 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/2006 ,  C23C18/204 ,  C23C18/2086 ,  C23C18/30 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C25D3/38 ,  C25D5/34 ,  C25D5/54 ,  C25D5/56 ,  H05K3/381 ,  H05K3/387 ,  H05K3/388

Abstract: Provided is a method of improving adhesion between a polymer substrate and a metal layer formed on the substrate. The method according to present invention includes (a) performing a surface modification treatment on a polymer film, (b) forming a metal layer on the surface modification treated polymer film, and (c) performing at least one selected from an aging treatment or a current application treatment on the metal layer.

Abstract translation: 提供了改善聚合物基材和形成在基材上的金属层之间的粘附性的方法。 根据本发明的方法包括（a）对聚合物膜进行表面改性处理，（b）在表面改性处理的聚合物膜上形成金属层，和（c）进行选自老化处理或 目前在金属层上的应用处理。

公开(公告)号：US09148953B2

公开(公告)日：2015-09-29

申请号：US14046408

申请日：2013-10-04

Applicant: Tyco Electronics Japan G. K.

Inventor： Katsunori Fukuda ,  Akira Torigoe

IPC: H05K1/03 ,  H05K3/24 ,  H05K3/38

CPC classification number: H05K1/0306 ,  H05K3/246 ,  H05K3/387 ,  H05K2201/0212 ,  H05K2201/0215 ,  H05K2201/0239

Abstract: A glass wiring board is provided that includes a glass substrate and a primer layer. The prime layer is disposed on the glass substrate and includes an intermediate layer and a copper plating layer disposed on the intermediate layer. The intermediate layer includes a resin coupling agent and a metal element dispersed in the resin coupling agent.

Abstract translation: 提供一种玻璃布线板，其包括玻璃基板和底漆层。 主层设置在玻璃基板上，并且包括设置在中间层上的中间层和镀铜层。 中间层包括树脂偶联剂和分散在树脂偶联剂中的金属元素。

公开(公告)号：US20150083602A1

公开(公告)日：2015-03-26

申请号：US14373961

申请日：2013-02-06

Applicant: Atotech Deutschland GmbH

Inventor： Richard Nichols ,  Don Jang ,  Harald Riebel ,  Frank Brüning

IPC: H05K3/38 ,  H05K3/06 ,  C25D7/06 ,  C23C18/40

CPC classification number: H05K3/387 ,  C23C18/1653 ,  C23C18/2006 ,  C23C18/2066 ,  C23C18/30 ,  C23C18/40 ,  C23C18/405 ,  C25D3/38 ,  C25D5/022 ,  C25D5/56 ,  C25D7/00 ,  C25D7/06 ,  H05K3/06 ,  H05K3/108 ,  H05K3/381 ,  H05K3/388 ,  H05K3/389 ,  H05K3/421 ,  H05K3/4644 ,  H05K2203/0789 ,  H05K2203/0793 ,  H05K2203/0796

Abstract: The present invention relates to a method for manufacture of fine line circuitry in the manufacture of printed circuit boards, IC substrates and the like. The method utilizes a first conductive layer on the smooth surface of a build-up layer and a second conductive layer selected from electrically conductive polymers, colloidal noble metals and electrically conductive carbon particles on the roughened walls of at least one opening which are formed after depositing the first conductive layer.

Abstract translation: 本发明涉及制造印刷电路板，IC基板等中的细线电路的制造方法。 该方法利用堆积层的光滑表面上的第一导电层和选自导电聚合物，胶体贵金属和在沉积后形成的至少一个开口的粗糙化壁上的导电碳颗粒的第二导电层 第一导电层。

公开(公告)号：US08822830B2

公开(公告)日：2014-09-02

申请号：US13432471

申请日：2012-03-28

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having circuits on one surface of the first insulating layer, a second conductor layer having circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes formed in openings of the first and second insulating layers and made of conductive materials filling the openings such that circuits in the first and third conductor layers are connected to one or more circuits in the second conductor layer, and the first and second via holes have bottom ends facing the second conductor layer and top ends larger than the bottom ends.

Abstract translation: 一种多层印刷电路板，包括第一绝缘层，在第一绝缘层的一个表面上具有电路的第一导体层，在第一绝缘层的相对表面上具有电路的第二导体层，第二绝缘层， 第二导体和第一绝缘层，以及在第二导体层的相对侧的第二绝缘层上具有电路的第三导体层。 第一和第二绝缘层具有形成在第一和第二绝缘层的开口中的第一和第二通孔，并由填充开口的导电材料制成，使得第一和第三导体层中的电路连接到第二和第二绝缘层中的一个或多个电路 导体层，第一和第二通孔具有面向第二导体层的底端，并且顶端大于底端。

公开(公告)号：US08782882B2

公开(公告)日：2014-07-22

申请号：US13169736

申请日：2011-06-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H01K3/10

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method of manufacturing a printed circuit board includes the following steps (A) to (D). (A) Laminating a resin insulating layer on each of two sides of a core member to form a core substrate, (B) forming penetrating openings in the core substrate by applying laser beams, (C) forming a rough surface on the core substrate, and (D) providing a metal film for each penetrating opening to form through holes.

Abstract translation: 制造印刷电路板的方法包括以下步骤（A）至（D）。 （A）在芯部件的两侧各自层叠树脂绝缘层，形成芯基板，（B）通过施加激光而在芯基板上形成贯通孔，（C）在芯基板上形成粗糙面， 和（D）为每个穿透孔提供金属膜以形成通孔。

公开(公告)号：US20130062108A1

公开(公告)日：2013-03-14

申请号：US13604833

申请日：2012-09-06

Applicant: Hitoshi KONDO

Inventor： Hitoshi KONDO

IPC: H05K3/46 ,  H05K1/11 ,  H05K1/00 ,  B82Y99/00 ,  B82Y30/00

CPC classification number: H05K3/387 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2924/01322 ,  H05K3/205 ,  H05K3/388 ,  H05K3/4069 ,  H05K3/4682 ,  H05K2201/0195 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A wiring board includes: a first wiring layer; a first insulating layer formed on the first wiring layer and including a reinforcing material therein, the first insulating layer having a first opening; a contact layer formed on the first insulating layer and having a second opening communicated with the first opening; and a second wiring layer comprising a second via and a second wiring pattern connected to the second via. The second wiring pattern is formed on the contact layer, and the second via is filled in the first and second openings. An adhesion property between the contact layer and the second wiring pattern is higher than that between the first insulating layer and the second wiring pattern, and a thickness of the contact layer is smaller than that of the first insulating layer.

Abstract translation: 布线板包括：第一布线层; 第一绝缘层，形成在所述第一布线层上并且在其中包括增强材料，所述第一绝缘层具有第一开口; 形成在所述第一绝缘层上并且具有与所述第一开口连通的第二开口的接触层; 以及第二布线层，包括连接到第二通孔的第二通孔和第二布线图案。 第二布线图案形成在接触层上，第二通孔填充在第一和第二开口中。 接触层和第二布线图案之间的粘附性高于第一绝缘层和第二布线图案之间的粘附性，并且接触层的厚度小于第一绝缘层的厚度。

公开(公告)号：US08288665B2

公开(公告)日：2012-10-16

申请号：US12913258

申请日：2010-10-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/11

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having conductor circuits on one surface of the first insulating layer, a second conductor layer having conductor circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having conductor circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes which are formed in openings of the first and second insulating layers and made of conductive materials filled to the top of the openings such that conductor circuits in the first and third conductor layers are connected to one or more conductor circuits in the second conductor layer, and the first and second via holes are tapering toward the second conductor layer.

Abstract translation: 一种多层印刷电路板，包括第一绝缘层，在第一绝缘层的一个表面上具有导体电路的第一导体层，在第一绝缘层的相对表面上具有导体电路的第二导体层，第二绝缘层 在第二导体和第一绝缘层上的第二绝缘层和在第二导体层的相对侧的第二绝缘层上具有导体电路的第三导体层。 第一绝缘层和第二绝缘层具有第一和第二通孔，其形成在第一和第二绝缘层的开口中，并由填充到开口顶部的导电材料制成，使得第一和第三导体层中的导体电路连接到 第二导体层中的一个或多个导体电路，以及第一和第二通孔朝向第二导体层逐渐变细。

公开(公告)号：US08273463B2

公开(公告)日：2012-09-25

申请号：US12427761

申请日：2009-04-22

Applicant: Mitsuyuki Tsurumi

Inventor： Mitsuyuki Tsurumi

IPC: B32B27/00 ,  B32B15/08 ,  C08J7/04 ,  C23C18/16

CPC classification number: H05K3/387 ,  C23C18/1653 ,  C23C18/2086 ,  H05K2203/066 ,  Y10T428/31681 ,  Y10T428/31721

Abstract: Disclosed is a multilayer film for plating comprising, on a surface of a first substrate, a plating receptive layer which contains a polymer having a polymerizable group and a functional group, wherein the plating receptive layer satisfies at least one of the following (1)-(4): (1) the saturated water absorption ratio is from 0.01 to 10% by mass in an environment of a temperature of 25° C. and relative humidity of 50%; (2) the saturated water absorption ratio is from 0.05 to 20% by mass in an environment of a temperature of 25° C. and relative humidity of 95%; (3) the water absorption ratio is from 0.1 to 30% by mass after immersion in boiling water at 100° C. for one hour; and (4) the surface contact angle of distilled water is from 50° to 150° after 5 μl of the distilled water is dropped onto the plating receptive layer and allowed to stand for 15 seconds in an environment of a temperature of 25° C. and relative humidity of 50%.

Abstract translation: 公开了一种用于电镀的多层膜，其包括在第一衬底的表面上含有具有聚合性基团和官能团的聚合物的电镀接受层，其中电镀接受层满足以下（1） - （4）：（1）在温度25℃，相对湿度50％的环境下，饱和吸水率为0.01〜10质量％ （2）在温度25℃，相对湿度95％的环境下，饱和吸水率为0.05〜20质量％。 （3）在100℃的沸水中浸渍1小时后，吸水率为0.1〜30质量％ 和（4）蒸馏水的表面接触角为50°〜150°后，将5μl蒸馏水滴入镀层，并在25℃的温度环境下静置15秒。 相对湿度为50％。