公开(公告)号：US08106518B2

公开(公告)日：2012-01-31

申请号：US12640766

申请日：2009-12-17

申请人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

发明人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/274 ,  H01L2224/81136 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1451 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

摘要翻译： 在层叠多个半导体芯片的半导体装置中，不会降低生产率而提高性能。 半导体器件具有多个元件，层间绝缘膜，焊盘和与依次形成在硅基板的主表面上的焊盘电连接的凸块电极，并且具有形成在硅衬底的背面上的背面电极 硅基板并与凸块电极电连接。 凸块电极具有贯穿焊盘并朝向硅衬底侧突出的突出部分。 背面电极形成为从硅衬底的背面侧朝向主面侧到达突起电极的突出部，并覆盖未到达的背面电极孔部的内部 垫，使得背面电极与凸块电极电连接。

公开(公告)号：US20120021563A1

公开(公告)日：2012-01-26

申请号：US13258664

申请日：2010-03-10

申请人： Mitsumasa Koyanagi ,  Takafumi Fukushima ,  Masahiko Sugiyama

发明人： Mitsumasa Koyanagi ,  Takafumi Fukushima ,  Masahiko Sugiyama

IPC分类号： H01L21/50 ,  B32B37/14 ,  B32B38/00 ,  B32B37/12

CPC分类号： H01L21/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2221/68318 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/06182 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83002 ,  H01L2224/83005 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83896 ,  H01L2224/921 ,  H01L2224/95001 ,  H01L2224/95146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15788 ,  Y10T156/1798 ,  H01L2924/00014 ,  H01L2924/00

摘要： There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.

摘要翻译： 提供了一种用于将芯片临时附接到转录底物的三维集成电路制造方法，并且当芯片被转移到支撑衬底时，可靠地将芯片从转录衬底上分离。 当芯片临时连接到转录底物时，通过蒸发芯片和转录底物之间的液体，芯片和转录底物的固体可以彼此附着。 因此，芯片可以临时安装到转录基片上，以便不会偏离其本身的位置。 此外，通过将芯片和支撑基板之间的粘合强度设置为高于芯片和转录基板之间的粘合强度，当芯片从转录基板转移到支撑基板时，可以将芯片从转录基板上牢固地分离。

公开(公告)号：US20120001334A1

公开(公告)日：2012-01-05

申请号：US13233626

申请日：2011-09-15

申请人： Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

发明人： Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

IPC分类号： H01L23/538 ,  H01L23/532

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.

摘要翻译： 集成电路结构包括半导体衬底; 在所述半导体衬底上的互连结构，其中所述互连结构包括顶部金属间电介质（IMD）; 穿过所述互连结构进入所述半导体衬底的开口; 开幕式的指挥; 以及具有彼此物理连接的垂直部分和水平部分的隔离层。 垂直部分位于开口的侧壁上。 水平部分直接在互连结构上方。 集成电路结构在顶部IMD和隔离层的水平部分之间垂直地没有钝化层。

公开(公告)号：US20110304349A1

公开(公告)日：2011-12-15

申请号：US12814140

申请日：2010-06-11

申请人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Margaret Simmons-Matthews ,  Jeff West

发明人： Daniel Joseph Stillman ,  James L. Oborny ,  William John Antheunisse ,  Norman J. Armendariz ,  Ramyanshu Datta ,  Margaret Simmons-Matthews ,  Jeff West

IPC分类号： G01R31/26 ,  H01L23/538 ,  G01R31/02 ,  H01L23/544

CPC分类号： H01L23/49833 ,  G01R31/2886 ,  H01L21/561 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/80001 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections.

摘要翻译： 仅电子组件的仅仅双面测试的方法包括提供连接到包括封装衬底的管芯支撑件的（TSV）裸片倒装芯片的经单片化的衬底。 TSV模具上的TSV从其前端延伸到其底部的可接触的TSV尖端。 TSV管芯前端的TSV与ML衬底的顶表面上的嵌入式顶层衬底焊盘耦合。 模具支撑件包括在嵌入的顶侧衬底焊盘的至少一部分和在模具区域的侧面的模具支撑件的顶侧表面上的侧向顶部焊盘之间的横向耦合路径。 可接触的TSV尖端与探针接触以提供与TSV的第一顶侧连接，并且横向顶部焊盘与探针接触以提供第二顶侧连接。 使用第一和第二顶部连接来执行电子组件的双面测试。

公开(公告)号：US20110300669A1

公开(公告)日：2011-12-08

申请号：US12795315

申请日：2010-06-07

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chia-Lin Hung ,  Ying-Sheng Chuang

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chia-Lin Hung ,  Ying-Sheng Chuang

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

摘要： The present invention relates to a method for making chip assemblies, including the following steps of: (a) providing a tested upper wafer and at least one tested lower wafer; (b) sawing the at least one tested lower wafer to form a plurality of lower dice, the lower dice including a plurality of know good lower dice; (c) picking up and rearranging the know good lower dice on a carrier according to the wafer map of the upper wafer; (d) bonding the upper wafer and the carrier; (e) removing the carrier; and (f) proceeding sawing step. Whereby, the dice of the die assembly are both known good dice, thus the yield loss caused by the different yields between the upper wafer and the lower wafer will not occur.

摘要翻译： 本发明涉及一种制造芯片组件的方法，包括以下步骤：（a）提供测试的上晶片和至少一个经测试的下晶片; （b）锯切所述至少一个经测试的下晶片以形成多个下骰子，所述下骰子包括多个熟知的较低骰子; （c）根据上晶片的晶片图拾取并重新排列载体上的已知的较好的下骰子; （d）粘合上晶片和载体; （e）清除载体; 和（f）进行锯切步骤。 由此，芯片组件的裸片都是已知的好的裸片，因此不会发生由上晶片和下晶片之间的不同产量引起的屈服损失。

公开(公告)号：US20110277655A1

公开(公告)日：2011-11-17

申请号：US12778867

申请日：2010-05-12

申请人： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B41F33/00

CPC分类号： H01L23/5384 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/525 ,  H01L23/5328 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

摘要翻译： 形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。 导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。 然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

公开(公告)号：US08048772B2

公开(公告)日：2011-11-01

申请号：US12502735

申请日：2009-07-14

申请人： Masayoshi Shiozaki ,  Makoto Moriguchi

发明人： Masayoshi Shiozaki ,  Makoto Moriguchi

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： B81C1/0023 ,  B81B2207/053 ,  B81C1/00238 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/50 ,  H01L21/76251 ,  H01L23/10 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/13009 ,  H01L2224/13144 ,  H01L2224/45124 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/0401

摘要： A substrate bonding method has a film forming step of forming an insulating film for bonding in such a manner that an SiO2 film made of TEOS is deposited on at least one of a first substrate and a second substrate by a CVD method, and a bonding step of bonding the first substrate and the second substrate with the insulating film for bonding being interposed between the first substrate and the second substrate.

摘要翻译： 基板接合方法具有：通过CVD法在由第一基板和第二基板的至少一个上淀积由TEOS构成的SiO 2膜的方式形成用于接合的绝缘膜的成膜工序;以及接合工序 在第一基板和第二基板之间插入用于接合的绝缘膜的第一基板和第二基板的接合。

公开(公告)号：US20110250720A1

公开(公告)日：2011-10-13

申请号：US13110144

申请日：2011-05-18

申请人： Satyendra Singh CHAUHAN

发明人： Satyendra Singh CHAUHAN

IPC分类号： H01L21/60

CPC分类号： H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/81136 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die.

摘要翻译： 管芯接合系统和方法包括具有前侧，后侧和通过硅通孔的完全填充的上模，从上模的后侧突出的完全填充的硅通孔的一部分。 下模包括前侧，后侧和部分填充的硅通孔，其形成为限定暴露于模具的前侧的通孔开口，部分填充的硅通孔的一部分从背面侧突出 下模。 互连通过硅通孔的上模的突出部分的外表面与下模具中的通孔开口的内表面结合。

公开(公告)号：US20110207322A1

公开(公告)日：2011-08-25

申请号：US13026830

申请日：2011-02-14

申请人： Masahiro YAMAGUCHI

发明人： Masahiro YAMAGUCHI

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L27/105 ,  H01L27/10894 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05094 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1162 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes, but is not limited to, the following processes. A seed layer is formed over a substrate. The seed layer includes first, second, and third portions. A first electrode covering the first portion of the seed layer is formed without forming an electrode on the second and third portions of the seed layer. The third portion of the seed layer is removed so that the first and second portions remain over the substrate, and the first and second portions are separated from each other.

摘要翻译： 制造半导体器件的方法包括但不限于以下处理。 种子层形成在衬底上。 籽晶层包括第一，第二和第三部分。 形成覆盖种子层的第一部分的第一电极，而不在种子层的第二和第三部分上形成电极。 去除种子层的第三部分，使得第一和第二部分保留在衬底上，并且第一和第二部分彼此分离。

公开(公告)号：US20110186990A1

公开(公告)日：2011-08-04

申请号：US12888135

申请日：2010-09-22

申请人： Kazuaki Mawatari ,  Kengo Aoya ,  Yoshikatsu Umeda ,  Jeffrey A. West

发明人： Kazuaki Mawatari ,  Kengo Aoya ,  Yoshikatsu Umeda ,  Jeffrey A. West

IPC分类号： H01L23/48

CPC分类号： H01L24/16 ,  H01L23/3677 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014

摘要： An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a semiconductor substrate including a topside semiconductor surface having active circuitry and a bottomside surface. The topside semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate. A plurality of TSVs include an inner metal core that extends from the topside semiconductor surface to protruding TSV tips which extend out from the bottomside surface. At least one of the plurality of TSVs are dummy TSVs that have their protruding TSV tips exclusive of any electrically connection thereto that provide additional surface area that enhances heat dissipation from the bottomside of the TSV die.

摘要翻译： 集成电路（IC）装置包括具有包括衬底焊盘的顶表面的衬底和包括半导体衬底的贯穿衬底通孔（TSV）裸片，该半导体衬底包括具有有源电路和底部表面的顶侧半导体表面。 顶侧半导体表面包括结合连接器，其连接到衬底的顶表面上的衬底焊盘。 多个TSV包括从顶侧半导体表面延伸到从底部表面延伸出的突出TSV尖端的内部金属芯。 多个TSV中的至少一个是具有突出的TSV尖端的虚拟TSV，其不提供任何与其电连接的TSV提供额外的表面积，从而增强了TSV管芯的底部散热。