公开(公告)号：US07414857B2

公开(公告)日：2008-08-19

申请号：US11588104

申请日：2006-10-26

Applicant: Andrew P. Ritter ,  John L. Galvagni

Inventor： Andrew P. Ritter ,  John L. Galvagni

IPC: H05H5/00

CPC classification number: H01G4/232 ,  H01C1/148 ,  H01C7/18 ,  H01G2/065 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/0792

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.

Abstract translation: 低电感电容器包括布置在电介质层之间并定向为使得电极基本上垂直于安装表面的电极。 垂直电极沿着器件外围露出，以确定在哪里形成终端焊盘，限定了焊盘之间的狭窄和可控的间距，用于减小电流环路面积，从而降低了元件电感。 可以通过叉指式终端来提供电流回路面积和部件等效串联电感（ESL）的进一步减小。 端接可以通过各种无电镀技术形成，并且可以直接焊接到电路板焊盘。 端子也可以位于电容器的“端部”上，以实现电气测试或控制焊接圆角尺寸和形状。 可以在设备的给定的底部（安装）表面上形成两端子器件以及具有多个端子的器件。 端子也可以形成在顶表面（与指定的安装表面相对）上，并且可以是镜像，反向镜像或相对于底表面的不同形状。

公开(公告)号：US20080079139A1

公开(公告)日：2008-04-03

申请号：US11541124

申请日：2006-09-29

Applicant: Chunfei Ye ,  Boping Wu

Inventor： Chunfei Ye ,  Boping Wu

IPC: H01L23/12 ,  H01L21/00

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/0792 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: In some embodiments, a micro-via structure design for high performance integrated circuits is presented. In this regard, an integrated circuit chip package is introduced having a dielectric layer, a plated throughhole in the dielectric layer, and a micro-via coupled with the plated throughhole, wherein the micro-via forms a path around an axis. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提出了用于高性能集成电路的微通孔结构设计。 在这方面，引入集成电路芯片封装，其具有电介质层，电介质层中的电镀通孔和与电镀通孔耦合的微通孔，其中微通孔围绕轴线形成路径。 还公开并要求保护其他实施例。

公开(公告)号：US20080011938A1

公开(公告)日：2008-01-17

申请号：US11672629

申请日：2007-02-08

Applicant: Michihide SASADA ,  Osamu Kagaya ,  Yukitoshi Okamura

Inventor： Michihide SASADA ,  Osamu Kagaya ,  Yukitoshi Okamura

IPC: H01J40/14

CPC classification number: H01L25/167 ,  H01L2224/48137 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0243 ,  H05K1/189 ,  H05K3/306 ,  H05K2201/0191 ,  H05K2201/0792 ,  H05K2201/10121 ,  H05K2201/10424 ,  H05K2201/2036 ,  H01L2924/00

Abstract: A photodetector module that can achieve impedance matching and power saving. A photodetector (11) and an amplifier (12) for amplifying an electric signal from the photodetector (11) are mounted on a stem (14). A dielectric plate (18) is arranged between the stem (14) and a flexible substrate (20). To transfer an electric signal from the amplifier (12) to the substrate (20), a lead pin (15d) is provided to pass through the stem (14) and the dielectric plate (18). The output of the amplifier (12) includes a capacitance component, and the output impedance of the amplifier (12) is higher than the impedance that matches with the substrate (20). Further, the thickness d of the dielectric plate (18) is such that the inductance component of the lead pin (15d) includes an inductance component that is inductive, which cancels the capacitance component of the amplifier, and impedance matching with the substrate (20) can be achieved.

Abstract translation: 可以实现阻抗匹配和省电的光电检测器模块。 用于放大来自光电检测器（11）的电信号的光电检测器（11）和放大器（12）安装在杆（14）上。 电介质板（18）设置在杆（14）和柔性衬底（20）之间。 为了将电信号从放大器（12）传送到衬底（20），提供引脚（15d）以穿过杆（14）和电介质板（18）。 放大器（12）的输出包括电容分量，放大器（12）的输出阻抗高于与衬底（20）匹配的阻抗。 此外，电介质板（18）的厚度d使得引脚（15d）的电感分量包括感应的电感分量，其抵消放大器的电容分量和与衬底的阻抗匹配（ 20）。

公开(公告)号：US07312402B2

公开(公告)日：2007-12-25

申请号：US10269404

申请日：2002-10-11

Applicant: Rafael Antu ,  Cathy Marie Drews ,  David A. Plomgren ,  Todd Edward Takken

Inventor： Rafael Antu ,  Cathy Marie Drews ,  David A. Plomgren ,  Todd Edward Takken

IPC: H05K1/16 ,  H01K3/10

CPC classification number: H05K1/0231 ,  H05K1/114 ,  H05K2201/0792 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49133 ,  Y10T29/49165

Abstract: A method and apparatus that provides improved loop inductance of decoupling capacitors. Vias are moved close to the pads and close to each other. Instead of placing power and ground vias on opposite sides of the capacitor, these vias are moved around to the same side of the capacitor and are placed as close to each other as manufacturing tolerances will allow. For designs using standard two-terminal surface mount capacitors, two vias per capacitor, and standard manufacturing procedures (no vias inside pads, for example), the lowest possible loop inductance of the capacitor's connections to the printed circuit board planes is provided. This results in the lowest effective capacitor series input inductance.

Abstract translation: 提供去耦电容的环路电感的方法和装置。 通风口移动靠近垫子并彼此靠近。 代替在电容器的相对侧上放置电源和接地通孔，这些通孔被移动到电容器的同一侧，并且如制造公差将允许的那样放置得彼此靠近。 对于使用标准两端表面贴装电容器的设计，每个电容器有两个通孔，以及标准制造程序（例如，焊盘内部没有通孔），提供了电容器与印刷电路板平面连接的最低环路电感。 这导致最低有效的电容器串联输入电感。

公开(公告)号：US07276668B2

公开(公告)日：2007-10-02

申请号：US10964619

申请日：2004-10-15

Applicant: Sheng-Yuan Lee ,  Ya-Chi Liao

Inventor： Sheng-Yuan Lee ,  Ya-Chi Liao

IPC: H05K1/03

CPC classification number: H05K1/025 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A circuit board with mounting pads is described for improving the frequency response of routing traces. The present invention is used to etch an etching hole on ground layer corresponding to the surface-mounted devices (SMD) on a routing layer and therefore the parasitic effect from the stray capacitor is reduced, resulting in eliminating the parasitic effect in high-frequency and raising the quality of the PCB as well.

Abstract translation: 描述了具有安装焊盘的电路板，用于改善路由迹线的频率响应。 本发明用于蚀刻对应于路由层上的表面安装器件（SMD）的接地层上的蚀刻孔，因此来自杂散电容器的寄生效应降低，从而消除了高频下的寄生效应， 提高PCB的质量。

公开(公告)号：US20070145551A1

公开(公告)日：2007-06-28

申请号：US11567804

申请日：2006-12-07

Applicant: Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

Inventor： Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

IPC: H01L23/02

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12. Vias 36 are arranged immediately above the bump terminals 16, and clearance holes 34, the diameter of which is smaller than the diameter of the bump terminals 16, are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

Abstract translation: 提供了具有优异的高频特性并且可以获得用于内部布线图案的大面积的半导体封装。 根据本发明，半导体封装包括：安装在多层布线板12的正面上的多层印刷布线板12和IC芯片以及安装在反面上的多个凸点端子16。 每个凸块端子16包括具有平坦面40的绝缘芯42和沉积在除了平面40之外的所有外表面上的导电涂层。 导电涂层44的端面看起来像围绕绝缘芯42的环，并且被焊接到形成在多层印刷线路板12的背面上的环形连接焊盘52。 通孔36布置在凸块端子16的正上方，并且其直径小于凸点端子16的直径的间隙孔34形成在内部布线图形28和30中以允许通孔36通过。

公开(公告)号：US20070096254A1

公开(公告)日：2007-05-03

申请号：US11588104

申请日：2006-10-26

Applicant: Andrew Ritter ,  John Galvagni

Inventor： Andrew Ritter ,  John Galvagni

IPC: H01L29/00 ,  H01G4/30

CPC classification number: H01G4/232 ,  H01C1/148 ,  H01C7/18 ,  H01G2/065 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/0792

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.

Abstract translation: 低电感电容器包括布置在电介质层之间并定向为使得电极基本上垂直于安装表面的电极。 垂直电极沿着器件外围露出，以确定在哪里形成终端焊盘，限定了焊盘之间的狭窄和可控的间距，用于减小电流环路面积，从而降低了元件电感。 可以通过叉指式终端来提供电流回路面积和部件等效串联电感（ESL）的进一步减小。 端接可以通过各种无电镀技术形成，并且可以直接焊接到电路板焊盘。 端子也可以位于电容器的“端部”上，以实现电气测试或控制焊接圆角尺寸和形状。 可以在设备的给定底部（安装）表面上形成两端子器件以及具有多个端子的器件。 端子也可以形成在顶表面（与指定的安装表面相对）上，并且可以是镜像，反向镜像或相对于底表面的不同形状。

公开(公告)号：US20070093107A1

公开(公告)日：2007-04-26

申请号：US11585959

申请日：2006-10-25

Applicant: Kenji Motohashi ,  Takashi Yanagimoto ,  Hideji Miyanishi ,  Kazumasa Aoki

Inventor： Kenji Motohashi ,  Takashi Yanagimoto ,  Hideji Miyanishi ,  Kazumasa Aoki

IPC: H01R29/00

CPC classification number: H05K1/117 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A design rule for a printed wiring board is provided. A conductive layer and a pad are separate from each other in a distance defined by the design rule, which sufficiently prevents the capacitance coupling between the conductive layer and the pad.

Abstract translation: 提供印刷电路板的设计规则。 导电层和焊盘在由设计规则限定的距离内彼此分开，这足以防止导电层和焊盘之间的电容耦合。

公开(公告)号：US20060227522A1

公开(公告)日：2006-10-12

申请号：US11105141

申请日：2005-04-11

Applicant: Chung-Chi Huang ,  Richard Kunze ,  Beom-Taek Lee

Inventor： Chung-Chi Huang ,  Richard Kunze ,  Beom-Taek Lee

IPC: H05K7/06 ,  H05K1/11

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/0949 ,  H05K2201/1003 ,  H05K2201/10325 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A component having an inductor to at least partially compensate for a capacitance in a circuit of the component, is described herein.

公开(公告)号：US20060145308A1

公开(公告)日：2006-07-06

申请号：US11029518

申请日：2005-01-05

Applicant: Brian Floyd ,  Ullrich Pfeiffer ,  Scott Reynolds

Inventor： Brian Floyd ,  Ullrich Pfeiffer ,  Scott Reynolds

IPC: H01L39/00

CPC classification number: H05K1/111 ,  H01L23/5225 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06051 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19051 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P5/02 ,  H05K1/0237 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/09781 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Shielded circuit pad is provided where the parasitic capacitance is tuned out by the inclusion of a shunt transmission line stub which reduces the substrate induced loss in millimeter-wave applications. The circuit pad is located on the substrate, with a shield located beneath the circuit pad, and the shunt transmission line stub attached to the circuit pad. Accordingly, controlled impedance is obtained for millimeter-wave applications. The spacing between the circuit pad and the shield may then be minimized.