公开(公告)号：US10050074B2

公开(公告)日：2018-08-14

申请号：US15167348

申请日：2016-05-27

申请人： Sony Corporation

发明人： Yoshihiro Nabe ,  Hiroshi Asami ,  Yuji Takaoka ,  Yoshimichi Harada

IPC分类号： H01L23/02 ,  H01L27/146 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L31/0224

摘要： A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

公开(公告)号：US10037945B2

公开(公告)日：2018-07-31

申请号：US14860723

申请日：2015-09-22

申请人： WIN Semiconductors Corp.

发明人： Chih-Wen Huang ,  Jui-Chieh Chiu ,  Fan-Hsiu Huang

IPC分类号： H01L23/02 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/31 ,  H01L23/66

CPC分类号： H01L23/5384 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L25/0657 ,  H01L2223/6683 ,  H01L2224/48091 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the at least a lead, where at least a first hole is formed through the at least a routing layer; a die, disposed on the at least a routing layer, where at least a second hole is formed through the die, and the die generates or receives the at least a signal; and a molding cap, for covering the at least a routing layer and the die; where the at least a signal is delivered through the at least a first hole and the at least a second hole.

公开(公告)号：US10028380B2

公开(公告)日：2018-07-17

申请号：US14521303

申请日：2014-10-22

申请人： SanDisk Technologies Inc.

发明人： Abhishek Ramesh Tambat ,  Naveen Kini ,  Elad Baram ,  Pradip Ghimire

IPC分类号： H01L23/02 ,  H05K1/11 ,  H01L23/498 ,  H05K1/18 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

摘要： A semiconductor package such as a multi-chip package is disclosed. The semiconductor package may be configured for dual second level interconnection onto a printed circuit board of a host device. Thus, a single semiconductor package may be used on host printed circuit boards having different configurations.

公开(公告)号：US10026467B2

公开(公告)日：2018-07-17

申请号：US15337323

申请日：2016-10-28

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC分类号： G11C5/06 ,  G11C11/408 ,  G11C8/18 ,  H01L25/065 ,  H01L25/18 ,  H01L23/64 ,  H01L23/31 ,  G11C11/409 ,  H01L23/02

CPC分类号： G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

公开(公告)号：US10014292B2

公开(公告)日：2018-07-03

申请号：US15477106

申请日：2017-04-02

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist

IPC分类号： H01L23/02 ,  H01L27/06 ,  H01L25/07 ,  H01L25/11 ,  H01L21/683 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L23/544 ,  H01L25/071 ,  H01L25/117 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L2221/68368 ,  H01L2223/54426 ,  H01L2224/18

摘要： A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die.

公开(公告)号：US10008475B2

公开(公告)日：2018-06-26

申请号：US13629368

申请日：2012-09-27

申请人： Intel Corporation

发明人： Chia-Pin Chiu

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/065 ,  H01L23/13 ,  H01L23/36 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/29109 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00012 ,  H01L2924/1515 ,  H01L2924/15321 ,  H01L2924/171 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include a substrate, a first die, and a second die coupled to the first die and the substrate. The substrate may include an opening. At least a portion of the die may occupy at least a portion of the opening in the substrate. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US09966320B2

公开(公告)日：2018-05-08

申请号：US15270145

申请日：2016-09-20

申请人： RAYTHEON COMPANY

发明人： Roland W. Gooch ,  Buu Q. Diep ,  Adam M. Kennedy ,  Stephen H. Black ,  Thomas A. Kocian

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/10 ,  H01L23/498 ,  H01L21/768 ,  B81B7/00 ,  H01L23/26 ,  H01L27/146 ,  B81C1/00 ,  H01L21/52

CPC分类号： H01L23/10 ,  B81B7/0038 ,  B81B2201/0207 ,  B81C1/00269 ,  B81C2203/035 ,  H01L21/52 ,  H01L21/76841 ,  H01L23/26 ,  H01L23/49866 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/1469 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

公开(公告)号：US09961782B2

公开(公告)日：2018-05-01

申请号：US15642037

申请日：2017-07-05

申请人： Kateeva, Inc.

发明人： Digby Pun ,  David C. Darrow ,  Robert B. Lowrance ,  Alexander Sou-Kang Ko

IPC分类号： H01L21/67 ,  H01L21/68 ,  B05C5/02 ,  H01L23/02 ,  H01L23/28 ,  H05K3/46 ,  B05D5/12 ,  B41J29/393 ,  B41J2/01 ,  H01L21/683

CPC分类号： H05K3/4644 ,  B05C5/0208 ,  B05D5/12 ,  B41J2/01 ,  B41J3/407 ,  B41J13/0027 ,  B41J29/393 ,  H01L21/67 ,  H01L21/6715 ,  H01L21/6776 ,  H01L21/67784 ,  H01L21/68 ,  H01L21/683 ,  H05K3/4679 ,  H05K2203/0104 ,  H05K2203/013 ,  H05K2203/0736 ,  H05K2203/166

摘要： A printer deposits material onto a substrate as part of a manufacturing process for an electronic product. At least one mechanical component experiences mechanical error, which is mitigated using transducers that equalize position of a transported thing, e.g., to provide an “ideal” conveyance path; a substrate conveyance system and/or a printhead conveyance system can each use transducers in this manner to improve precise droplet placement. In one embodiment, errors are measured in advance, with corrections being “played back” during production runs to mitigate repeatable transport path error. In a still more detailed embodiment, the transducers can be predicated on voice coils, which cooperate with a floatation table and floating, mechanical pivot assembly to provide frictionless, but mechanically-supported error correction.

公开(公告)号：US09960146B1

公开(公告)日：2018-05-01

申请号：US15462906

申请日：2017-03-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po-Chun Lin

IPC分类号： H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/92143 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor structure includes a first stacking interposer. The first stacking interposer includes a first interposer having a first surface and a second surface opposite thereto; a plurality of first conductive pillars penetrating through the first interposer from the first surface to the second surface; a plurality of first bumps disposed at a side of the first surface of the first interposer and electrically connected to the first conductive pillars; and a first redistribution layer disposed on the second surface of the first interposer. The first surface has a clearance region where is free of the first bumps. A first chip is disposed over the first redistribution layer. The first chip is aligned with the clearance region of the first surface of the first interposer in a direction perpendicular to the first surface. A plurality of second bumps interconnecting the first redistribution layer with the first chip.

公开(公告)号：US09917067B1

公开(公告)日：2018-03-13

申请号：US15419280

申请日：2017-01-30

申请人： KULITE SEMICONDUCTOR PRODUCTS, INC.

发明人： Sorin Stefanescu

IPC分类号： H01L23/06 ,  H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/45144 ,  H01L2224/45169 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/351 ,  H01L2924/365

摘要： Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.