公开(公告)号：US09536982B1

公开(公告)日：2017-01-03

申请号：US14930895

申请日：2015-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L29/51 ,  H01L21/31 ,  H01L29/78 ,  H01L29/423 ,  H01L21/283 ,  H01L21/768 ,  H01L23/522 ,  H01L21/764 ,  H01L21/8238

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract translation: 一种在半导体器件的沟道区上包括栅极结构的半导体器件。 源极和漏极区域可以存在于沟道区域的相对侧上。 半导体器件还可以包括存在于栅极结构的侧壁上的复合栅极侧壁间隔物。 复合栅极侧壁间隔物可以包括其中封装有气隙的第一组合物部分和完全固体并存在于第一组合物部分顶部的第二组合物部分。

公开(公告)号：US09472402B2

公开(公告)日：2016-10-18

申请号：US14487213

申请日：2014-09-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deok-kee Kim ,  Kenneth T. Settlemyer, Jr. ,  Kangguo Cheng ,  Ramachandra Divakaruni ,  Carl J. Radens ,  Dirk Pfeiffer ,  Timothy J. Dalton ,  Katherina E. Babich ,  Arpan P. Mohorowala ,  Harald Okorn-Schmidt

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  G03F7/11

CPC classification number: H01L21/0337 ,  G03F7/11 ,  H01L21/027 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/0338 ,  H01L21/31144

Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

公开(公告)号：US20160293706A1

公开(公告)日：2016-10-06

申请号：US15186632

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: A FinFET device includes a substrate, a gate structure positioned above the substrate, and sidewall spacers positioned adjacent to the gate structure. An epi semiconductor material is positioned in source and drain regions of the FinFET device and laterally outside of the sidewall spacers. A fin extends laterally under the gate structure and the sidewall spacers in a gate length direction of the FinFET device, wherein the end surfaces of the fin abut and engage the epi semiconductor material. A stressed material is positioned in a channel cavity located below the fin, above the substrate, and laterally between the epi semiconductor material, the stressed material having a top surface that abuts and engages a bottom surface of the fin, a bottom surface that abuts and engages the substrate, and end surfaces that abut and engage the epi semiconductor material.

Abstract translation: FinFET器件包括衬底，位于衬底上方的栅极结构以及邻近栅极结构定位的侧壁间隔物。 外延半导体材料位于FinFET器件的源极和漏极区域中，并且横向在侧壁间隔物的外侧。 翅片在FinFET器件的栅极长度方向上在栅极结构和侧壁间隔物之下横向延伸，其中鳍片的端面抵靠并接合外延半导体材料。 应力材料定位在位于翅片下方的衬底上方的通道腔中，并且横向地位于外延半导体材料之间，受压材料具有邻接并接合翅片的底表面的顶表面，邻接的底表面和 接合基板以及邻接和接合外延半导体材料的端面。

公开(公告)号：US09461042B2

公开(公告)日：2016-10-04

申请号：US14746017

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

公开(公告)号：US09437501B1

公开(公告)日：2016-09-06

申请号：US14861326

申请日：2015-09-22

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L27/092 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

Abstract translation: 制造纳米线器件的方法包括在衬底上设置第一纳米线堆叠，第一纳米线堆叠包括第一和第二半导体材料的交替层，第一半导体材料与衬底接触，第二半导体材料是暴露表面; 在所述衬底上设置第二纳米线堆叠，所述第二纳米线堆叠包括所述第一和第二半导体材料的交替层，所述第一半导体材料与所述衬底接触，所述第二半导体材料为暴露表面; 沿着第一纳米线堆叠上的第一栅极区域的侧壁形成第一栅极间隔物，并且沿着第二纳米线堆叠件上的第二栅极区域的侧壁形成第二栅极间隔物; 氧化所述第一栅极间隔物内的所述第一纳米线堆叠的一部分; 以及从所述第一纳米线堆叠和所述第二纳米线堆叠中去除所述第一半导体材料。

公开(公告)号：US09431306B2

公开(公告)日：2016-08-30

申请号：US15075437

申请日：2016-03-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/02 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.

Abstract translation: 一种方法包括形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一层，在第一层的上表面上方的翅片的相对侧上形成侧壁隔离物，去除第一层并执行 翅片修剪蚀刻工艺以限定多个增大尺寸的沟槽。 该方法还包括在增大尺寸的沟槽中形成绝缘材料的第一氧化阻挡层，在氧化阻挡层上方形成第二层绝缘材料，并进行热退火工艺以将部分的至少一部分 与第二绝缘材料层接触的鳍片形成氧化物鳍片隔离区域。

公开(公告)号：US09425319B2

公开(公告)日：2016-08-23

申请号：US14551606

申请日：2014-11-24

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。

公开(公告)号：US09425080B2

公开(公告)日：2016-08-23

申请号：US14600229

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Robert H. Dennard ,  Hemanth Jagannathan ,  Ali Khakifirooz ,  Tak H. Ning ,  Ghavam G. Shahidi

IPC: H01L21/762 ,  H01L27/115 ,  B82Y10/00 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L21/76251 ,  B82Y10/00 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11536 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881

Abstract: Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.

公开(公告)号：US09412822B2

公开(公告)日：2016-08-09

申请号：US14200737

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ajey P. Jacob ,  Witold P. Maszara

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

Abstract translation: 所公开的一种方法包括用蚀刻停止材料覆盖初始翅片结构的顶表面和侧壁的一部分，围绕初始翅片结构形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物， 去除牺牲栅极结构，其中蚀刻停止材料就位，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺，以移除位于替换下方的鳍结构的半导体衬底材料的一部分 门腔不被蚀刻停止材料覆盖，从而限定最终的翅片结构和位于最终翅片结构下方的通道腔，并且用应力材料基本上填充通道腔。

公开(公告)号：US20160225659A1

公开(公告)日：2016-08-04

申请号：US14608729

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/308 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76213 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/26506 ,  H01L21/3083 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成翅片，所述翅片具有包含氧化阻滞注入区域的下部第一部分和基本上不含氧化延迟注入区域的上部第二部分 在翅片的上部的相对侧上形成侧壁间隔物，形成邻近侧壁间隔物和鳍片下部的上部第二部分的第一绝缘材料层，并且第一绝缘材料层 位置，进行热退火处理以将与第一绝缘材料层接触的翅片的上部第二部分的部分转换成位于翅片的下部第一部分下方的翅片下方的氧化物翅片隔离区域。