公开(公告)号：US08368213B2

公开(公告)日：2013-02-05

申请号：US10935451

申请日：2004-09-07

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L23/485

CPC分类号： H01L24/12 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

公开(公告)号：USRE43674E1

公开(公告)日：2012-09-18

申请号：US11518595

申请日：2006-09-08

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L2924/0002 ,  H01L2924/00

摘要： A new post-passivation metal interconnect scheme is provided over the surface of a IC device that has been covered with a conventional layer of passivation. The metal scheme of the invention comprises, overlying a conventional layer of passivation, thick and wide metal lines in combination with thick layers of dielectric and bond pads. The interconnect system of the invention can be used for the distribution of power, ground, signal and clock lines from bond pads to circuits of a device that are provided in any location of the IC device without introducing significant power drop. No, or smaller ESD circuits are required due to the low impedance post-passivation interconnection, since any accumulated electrostatic discharge will be evenly distributed across all junction capacitance of the circuits on the chip. The post passivation metal scheme is connected to external circuits through bond pads, solder bonding, TAB bonding and the like. A top layer of the interconnect metal scheme is formed using a composite metal for purposes of wirebonding, the composite metal is created over a bulk conduction metal. A diffusion metal may be applied between the bulk metal and the composite metal, in addition a layer of Under-Barrier-Metal (UBM) may be required underneath the bulk conduction metal.

摘要翻译： 在已经被常规钝化层覆盖的IC器件的表面上提供了新的后钝化金属互连方案。 本发明的金属方案包括叠加常规的钝化层，厚和宽的金属线与厚的介电层和接合焊盘的组合。 本发明的互连系统可以用于将功率，接地，信号和时钟线从接合焊盘分配到设置在IC器件的任何位置的器件的电路，而不引入显着的功率下降。 由于低阻抗钝化后互连，不需要或更小的ESD电路，因为任何累积的静电放电将均匀分布在芯片上电路的所有结电容上。 后钝化金属方案通过接合焊盘，焊接，TAB接合等连接到外部电路。 互连金属方案的顶层使用用于引线键合的复合金属形成，复合金属在体导电金属上形成。 扩散金属可以施加在本体金属和复合金属之间，另外在体导电金属之下可能需要一层下阻挡金属（UBM）。

公开(公告)号：US08188603B2

公开(公告)日：2012-05-29

申请号：US11856076

申请日：2007-09-17

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

摘要翻译： 提供了一种创建互连线的方法。 细线互连提供在已经在衬底的表面中或其上形成的半导体电路的第一绝缘层中。 钝化层沉积在电介质层上，在钝化层的表面上形成厚的第二层电介质。 在厚的第二层电介质中产生厚而宽的互连线。 也可以消除第一层电介质，在已​​经沉积在衬底的表面上的钝化层的表面上产生宽厚的互连网络。

公开(公告)号：US08138079B2

公开(公告)日：2012-03-20

申请号：US11926154

申请日：2007-10-29

申请人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

摘要翻译： 提供了一种方法和结构，以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。 提供了具有有源和/或无源器件的半导体衬底，其中在有源和/或无源器件上形成互连金属化。 提供了形成在互连金属化之上的钝化层，其中在钝化层中形成开口以形成互连金属化的上金属层。 柔性金属焊盘形成在钝化层上方，其中柔性金属接合焊盘通过开口连接到上金属层，并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。 顺应性金属接合焊盘可以由复合金属结构形成。

公开(公告)号：US20110309473A1

公开(公告)日：2011-12-22

申请号：US13159190

申请日：2011-06-13

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L23/498

CPC分类号： H01L24/19 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

摘要翻译： 使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。 五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。 基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

公开(公告)号：US08022552B2

公开(公告)日：2011-09-20

申请号：US11766805

申请日：2007-06-22

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/3192 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/04953

摘要： A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5μm and 27 μm over a semiconductor substrate, and forming a passivation layer on the metal trace, wherein the passivation layer includes a layer of silicon nitride on the metal trace and a layer of silicon oxide on the layer of silicon nitride, or includes a layer of silicon oxynitride on the metal trace and a layer of silicon oxide on the layer of silicon oxynitride.

摘要翻译： 一种用于制造集成电路（IC）芯片的方法，包括在半导体衬底上形成厚度在5μm和27μm之间的金属迹线，并在金属迹线上形成钝化层，其中钝化层包括氮化硅层 在氮化硅层上的金属迹线和氧化硅层上，或者在金属迹线上包括一层氮氧化硅层，在氮氧化硅层上包括一层氧化硅。

公开(公告)号：US07960212B2

公开(公告)日：2011-06-14

申请号：US11842957

申请日：2007-08-22

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC分类号： H01L21/00

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

摘要翻译： 实现了制造芯片封装的方法。 在硅晶片上形成晶种层。 在种子层上形成光致抗蚀剂层，光致抗蚀剂层中的开口露出种子层。 在由开口暴露的种子层上形成第一焊料凸块。 去除光致抗蚀剂层。 不在第一焊料凸块下面的种子层被去除。 芯片上的第二焊料凸点与第一焊料凸块接合。

公开(公告)号：US07919873B2

公开(公告)日：2011-04-05

申请号：US12269064

申请日：2008-11-12

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC分类号： H01L29/40

CPC分类号： H01L25/50 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05624 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85399 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

公开(公告)号：US07915161B2

公开(公告)日：2011-03-29

申请号：US11856080

申请日：2007-09-17

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L21/4763

CPC分类号： H01L23/60 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/62 ,  H01L24/05 ,  H01L27/0248 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

公开(公告)号：US07906849B2

公开(公告)日：2011-03-15

申请号：US12032707

申请日：2008-02-18

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L28/10 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/02 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L27/0251 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2924/00

摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.