公开(公告)号：US20170200716A1

公开(公告)日：2017-07-13

申请号：US15470872

申请日：2017-03-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L27/06 ,  H01L23/367 ,  H01L23/00 ,  H01L27/088 ,  H01L23/58 ,  H01L23/528 ,  H01L23/544 ,  H01L23/522

CPC classification number: H01L27/0688 ,  H01L23/3677 ,  H01L23/544 ,  H01L23/552 ,  H01L23/562 ,  H01L23/585 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

公开(公告)号：US09691869B2

公开(公告)日：2017-06-27

申请号：US14880276

申请日：2015-10-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00 ,  H01L29/45 ,  H01L29/66 ,  H01L23/544 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L21/768 ,  H01L23/48 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/456 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66704 ,  H01L29/66772 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.

公开(公告)号：US20170179155A1

公开(公告)日：2017-06-22

申请号：US15452615

申请日：2017-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/11582 ,  H01L45/00 ,  H01L27/108

CPC classification number: H01L45/1206 ,  H01L21/76254 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/11578 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

公开(公告)号：US20170133395A1

公开(公告)日：2017-05-11

申请号：US15344562

申请日：2016-11-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/16 ,  G11C16/08 ,  G11C16/10 ,  H01L29/792 ,  G11C14/00

CPC classification number: H01L27/11568 ,  G11C11/5621 ,  G11C14/0018 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  H01L27/11565 ,  H01L28/00 ,  H01L29/7831 ,  H01L29/792 ,  H01L29/7923

Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.

公开(公告)号：US09640531B1

公开(公告)日：2017-05-02

申请号：US14607077

申请日：2015-01-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L23/48 ,  H01L23/50 ,  H01L23/552 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L27/0688 ,  H01L21/76254 ,  H01L21/76816 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/544 ,  H01L23/552 ,  H01L24/05 ,  H01L24/48 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L2223/54426 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlaying the first layer, the second layer including second transistors, where the second layer includes at least one thru layer via with a diameter less than 200 nm, where the second layer includes an oscillator, and where the oscillator has a frequency stability of less than 100 ppm error/° C.

公开(公告)号：US09613844B2

公开(公告)日：2017-04-04

申请号：US14821683

申请日：2015-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman ,  Israel Beinglass

IPC: H01L25/065 ,  H01L23/48 ,  H01L21/762 ,  H01L29/78 ,  H01L27/105 ,  H01L21/683 ,  H01L23/544 ,  H01L27/088 ,  G11C8/16 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/525 ,  H01L29/423 ,  H01L29/66 ,  H01L21/74 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.

公开(公告)号：US09496271B2

公开(公告)日：2016-11-15

申请号：US14506160

申请日：2014-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Yuniarto Widjaja

IPC: H01L27/115 ,  G11C16/02 ,  H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/412 ,  G11C16/04

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/412 ,  G11C16/02 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/10802 ,  H01L27/1104 ,  H01L27/115 ,  H01L27/11578 ,  H01L27/2436 ,  H01L29/7841

Abstract: A 3D IC based system, including: a first layer including first transistors; a second layer overlying the first layer, the second layer includes a plurality of second transistors, where the second layer includes at least one through second layer via having a diameter of less than 400 nm, and where at least one of the plurality of second transistors forms a two stable state memory cell including a back-bias region.

Abstract translation: 一种基于3D IC的系统，包括：包括第一晶体管的第一层; 覆盖第一层的第二层，第二层包括多个第二晶体管，其中第二层包括直径小于400nm的至少一个至第二层，并且其中多个第二晶体管中的至少一个 形成包括背偏置区域的两个稳定状态存储单元。

公开(公告)号：US09460978B1

公开(公告)日：2016-10-04

申请号：US13864243

申请日：2013-04-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/58 ,  H01L23/34 ,  H01L29/40

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并包括第二晶体管的第二层; 其中所述第二层包括直径小于150nm的贯通层通孔; 以及锁相环（PLL）电路，其中锁相环（PLL）电路连接到至少一个输入结构，并且其中至少一个输入结构被设计为将外部连接到设备的输入 设备。

公开(公告)号：US20160204085A1

公开(公告)日：2016-07-14

申请号：US15079017

申请日：2016-03-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 至少一个金属层，提供所述多个第一晶体管的至少一部分之间的互连; 第二层厚度小于2微米，第二层包括多个第二晶体管，第二层覆盖至少一个金属层; 以及构造成向第二晶体管的一部分提供功率的至少一个导电结构，其中所述提供功率由至少一个晶体管控制。

公开(公告)号：US20160064439A1

公开(公告)日：2016-03-03

申请号：US14936657

申请日：2015-11-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L25/0756 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/14647 ,  H01L27/1469 ,  H01L33/382

Abstract: A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

Abstract translation: 一种用于处理半导体晶片的方法，所述方法包括：提供包括包括多个图像传感器像素的图像传感器像素层的半导体晶片，覆盖晶片衬底的层; 然后将半导体晶片接合到载体晶片; 然后切断晶片衬底的大部分，然后处理晶片衬底的大部分以便重新使用。