公开(公告)号：US10163875B2

公开(公告)日：2018-12-25

申请号：US15915534

申请日：2018-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin ,  Yi-Hang Lin

IPC: H01L23/48 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48

Abstract: A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer.

公开(公告)号：US10157850B1

公开(公告)日：2018-12-18

申请号：US15662292

申请日：2017-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one die, conductive balls, and a molding compound. The at least one die and conductive balls are molded in a molding compound. Each of the conductive balls has a planar end portion and a non-planar end portion opposite to the planar end portion. A surface of the planar end portion of each of the conductive balls is substantially coplanar and levelled with a surface of the molding compound and a surface of the at least one die, and the non-planar end portion of each of the conductive balls protrudes from the molding compound.

公开(公告)号：US20180337137A1

公开(公告)日：2018-11-22

申请号：US16046399

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/53228 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

公开(公告)号：US10128226B2

公开(公告)日：2018-11-13

申请号：US15640684

申请日：2017-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/52 ,  H01L25/00 ,  H01L23/48 ,  H01L23/31 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The package structure also includes a conductive structure penetrating through the protection layer. The package structure further includes an interfacial layer between the protection layer and the conductive structure. The interfacial layer is made of an insulating material, and the interfacial layer is in direct contact with the protection layer. The interfacial layer extends across a back side of the semiconductor die.

公开(公告)号：US20180315733A1

公开(公告)日：2018-11-01

申请号：US15499901

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai ,  Chih-Chien Pan

IPC: H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/78 ,  H01L21/67

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/67207 ,  H01L21/78 ,  H01L24/02 ,  H01L24/13 ,  H01L24/14 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02379 ,  H01L2224/10145 ,  H01L2224/13024 ,  H01L2224/14181 ,  H01L2224/24146 ,  H01L2224/25171 ,  H01L2224/73259 ,  H01L2224/81007 ,  H01L2224/95001 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing.

公开(公告)号：US10115675B2

公开(公告)日：2018-10-30

申请号：US15235114

申请日：2016-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/60

Abstract: In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer conductive bump, a second package structure, a sealing material, and an electromagnetic interference (EMI) shielding layer. The first package structure has a first cut edge. The outer conductive bump is disposed on the first package structure and has a second cut edge. The second package structure is jointed onto the first package structure. The sealing material is disposed on the first package structure, surrounds the second package structure, and covers the outer conductive bump. The sealing material has a third cut edge. The EMI shielding layer contacts the first cut edge, the second cut edge and the third cut edge. The EMI shielding layer is electrically connected with the outer conductive bump.

公开(公告)号：US20180247900A1

公开(公告)日：2018-08-30

申请号：US15966382

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: Some embodiments relate to a semiconductor package. The semiconductor package includes a redistribution layer (RDL) including a first metal layer and a second metal layer. The second metal layer is stacked over the first metal layer and is coupled to the first metal layer through a via. A first semiconductor die is disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL, and the RDL enables fan-out connection of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die and over the RDL. The second semiconductor die is bonded to the RDL by a plurality of conductive bump structures.

公开(公告)号：US09929109B2

公开(公告)日：2018-03-27

申请号：US15389738

申请日：2016-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

公开(公告)号：US20170040290A1

公开(公告)日：2017-02-09

申请号：US15299961

申请日：2016-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Shang-Yun Hou

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6006 ,  H01L2021/6024 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05541 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.

Abstract translation: 提供一种半导体封装以及通过中介层形成具有一个或多个管芯的半导体封装的方法。 在一些实施例中，半导体封装具有延伸穿过插入器衬底的多个贯穿衬底通孔（TSV）。 重新分配结构布置在插入器基板的第一表面上，并且第一管芯结合到再分布结构。 第一管芯的边缘超过插入器衬底的最近边缘。 第二个管芯结合到再分布结构。 第二模具与第一模具横向分开一个空间。

公开(公告)号：US09236369B2

公开(公告)日：2016-01-12

申请号：US13945243

申请日：2013-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/30 ,  H01L25/00 ,  H01L27/06 ,  H01L21/822 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/8221 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is bonded to a third oxide layer of a second semiconductor substrate. The second part of first semiconductor substrate and the first oxide layer are removed to expose the first part of the first semiconductor substrate.

Abstract translation: 公开了一种包括以下概述的步骤的方法。 形成第一氧化物层以将第一半导体衬底分成第一部分和第二部分。 第二氧化物层形成在第一半导体衬底的第一部分上。 第一氧化物层结合到第二半导体衬底的第三氧化物层。 去除第一半导体衬底和第一氧化物层的第二部分以露出第一半导体衬底的第一部分。