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    Method and apparatus for supporting target-side security in a cache coherent system
    113.
    发明授权
    Method and apparatus for supporting target-side security in a cache coherent system 有权
    用于在高速缓存一致系统中支持目标侧安全性的方法和装置

    公开(公告)号：US08930638B2

    公开(公告)日：2015-01-06

    申请号：US13686604

    申请日：2012-11-27

    Applicant: QUALCOMM Technologies, Inc.

    Inventor： Laurent Moll ,  Jean-Jacques Lecler ,  Philippe Boucard

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/14 ,  G06F12/06 ,  G06F13/16

    CPC classification number: G06F12/0828 ,  G06F12/0676 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/14 ,  G06F12/1491 ,  G06F13/1642

    Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

    Abstract translation: 公开了一种高速缓存一致性控制器，包括该系统的系统及其操作方法。 一致性控制器确保目标端安全检查规则不被一致性控制器中通常使用的性能改进流程（如丢弃，合并，无效，转发和侦听）所违反。 这是通过确保标记为目标端安全检查的请求和任何其他重叠地址的请求直接转发到目标端安全过滤器而无需修改或副作用。

    Memory controller, memory system, semiconductor integrated circuit, and memory control method
    114.
    发明授权
    Memory controller, memory system, semiconductor integrated circuit, and memory control method 有权
    存储控制器，存储器系统，半导体集成电路和存储器控制方法

    公开(公告)号：US08918589B2

    公开(公告)日：2014-12-23

    申请号：US12988396

    申请日：2009-04-21

    Applicant: Koji Asai ,  Tetsuji Mochida ,  Daisuke Imoto ,  Takashi Yamada ,  Wataru Ohkoshi

    Inventor： Koji Asai ,  Tetsuji Mochida ,  Daisuke Imoto ,  Takashi Yamada ,  Wataru Ohkoshi

    IPC: G06F12/02 ,  G06F13/16 ,  G06F12/08 ,  G06F9/45

    CPC classification number: G06F13/1642 ,  G06F8/4442 ,  G06F12/0862 ,  G06F2212/6022

    Abstract: A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.

    Abstract translation: 根据本发明的存储器控​​制器（101）包括：命令产生单元（102），其基于包括指示图像数据中的矩形区域的逻辑地址的访问请求，生成包括物理地址的访问命令; 以及向存储器（0）发出由命令生成单元（102）生成的访问命令的命令发布单元（105）。 命令生成单元（102）包括：组决定单元（104），其基于与访问请求对应的物理地址，确定包含要访问的数据的存储体所属的组。 命令生成单元（102）生成一对第一和第二访问命令，当要访问的数据在属于不同组的两个存储体中是连续的时，共享一个属于不同组的两个存储体之间的预取缓冲器。

    Scheduler for memory
    115.
    发明授权
    Scheduler for memory 有权
    内存调度程序

    公开(公告)号：US08914571B2

    公开(公告)日：2014-12-16

    申请号：US13484337

    申请日：2012-05-31

    Applicant: Chul Lee

    Inventor： Chul Lee

    IPC: G06F12/00 ,  G06F13/16

    CPC classification number: G06F13/18 ,  G06F12/0607 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1668

    Abstract: A scheduler controls execution in a memory of operation requests received in an input request set (IRS) by providing a corresponding output request set (ORS). The scheduler includes zone standby units having a one-to-one relationship with corresponding zones such that each zone standby unit stores an operation request. The scheduler also includes an output processing unit that determines a processing sequence for the operation requests stored in the zone standby units to provide the ORS.

    Abstract translation: 调度器通过提供对应的输出请求集（ORS）来控制在输入请求集（IRS）中接收的操作请求的存储器中的执行。 调度器包括与相应区域具有一对一关系的区域备用单元，使得每个区域备用单元存储操作请求。 调度器还包括输出处理单元，其确定存储在区域备用单元中的操作请求的处理顺序以提供ORS。

    SYSTEM AND METHOD OF ARBITRATING CACHE REQUESTS
    116.
    发明申请
    SYSTEM AND METHOD OF ARBITRATING CACHE REQUESTS 有权
    仲裁请求的系统和方法

    公开(公告)号：US20140331012A1

    公开(公告)日：2014-11-06

    申请号：US13928169

    申请日：2013-06-26

    Applicant: QUALCOMM Incorporated

    Inventor： Chunlin Wang

    IPC: G06F12/08

    CPC classification number: G06F13/1642 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0855 ,  G06F13/1663 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/62

    Abstract: This disclosure relates to arbitration of different types of requests to access a cache. Features of this disclosure can be implemented in a graphics processing unit (GPU). In one embodiment, an arbiter can receive requests from a color processor and a depth processor and determine which of the received requests has the highest priority. The request with the highest priority can then be provided to the cache. The priority can be configurable. The arbiter can determine priority, for example, based on whether a location in the cache associated with a request is available, a weight associated with the request, a number of requests of a particular type processed by the arbiter, or any combination thereof.

    Abstract translation: 本公开涉及对访问高速缓存的不同类型的请求的仲裁。 本公开的特征可以在图形处理单元（GPU）中实现。 在一个实施例中，仲裁器可以接收来自颜色处理器和深度处理器的请求，并确定接收到的请求中哪一个具有最高优先级。 然后可以将具有最高优先级的请求提供给缓存。 优先级可以配置。 仲裁器可以例如基于与请求相关联的缓存中的位置是否可用，与请求相关联的权重，仲裁者处理的特定类型的请求数或其任何组合来确定优先级。

    QUEUE REQUEST ORDERING SYSTEMS AND METHODS
    118.
    发明申请
    QUEUE REQUEST ORDERING SYSTEMS AND METHODS 有权
    队列请求订单系统和方法

    公开(公告)号：US20140215181A1

    公开(公告)日：2014-07-31

    申请号：US13752161

    申请日：2013-01-28

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Kjeld SVENDSEN

    IPC: G06F12/10

    CPC classification number: G06F3/06 ,  G06F12/1018 ,  G06F13/1642

    Abstract: The described systems and methods can facilitate efficient and effective information storage. In one embodiment a system includes a hash component, a queue request order component and a request queue component. The hash component is operable to hash a request indication. The queue request order component is operable to track a queue request order. The request queue component is operable to queue and forward requests in accordance with direction from the queue request order component. In one embodiment, the storage component maintains a request without stalling a request in an aliasing condition.

    Abstract translation: 所描述的系统和方法可以促进有效和有效的信息存储。 在一个实施例中，系统包括散列组件，队列请求顺序组件和请求队列组件。 散列组件可操作以对请求指示进行散列。 队列请求命令组件可操作以跟踪队列请求顺序。 请求队列组件可用于根据队列请求命令组件的方向对请求进行排队和转发。 在一个实施例中，存储组件维持请求，而不会以混叠状态停止请求。

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