公开(公告)号：US11728400B2

公开(公告)日：2023-08-15

申请号：US17007579

申请日：2020-08-31

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  SMIC New Technology Research and Development (Shanghai) Corporation

发明人： Fei Zhou

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/84 ,  H01L29/78 ,  H01L21/822 ,  H01L29/165

CPC分类号： H01L29/42392 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8221 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78696 ,  H01L29/165

摘要： Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate, a plurality of fins protruding from the semiconductor substrate, an isolation layer formed on the fins and with a bandgap greater than a bandgap of the fins, and a first channel layer formed on the isolation layer and isolated from the isolation layer.

公开(公告)号：US11728174B2

公开(公告)日：2023-08-15

申请号：US17572807

申请日：2022-01-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Huan-Yung Yeh

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/3088 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

摘要： The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method includes forming an etching stop layer on a substrate, forming a target layer on the etching stop layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers.

公开(公告)号：US20230246077A1

公开(公告)日：2023-08-03

申请号：US18158342

申请日：2023-01-23

申请人： FUJI ELECTRIC CO., LTD.

发明人： Masakazu BABA ,  Shinsuke HARADA

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L21/308 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/1608 ,  H01L21/0262 ,  H01L21/308 ,  H01L21/02576 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/7813

摘要： A silicon carbide semiconductor device, including a semiconductor substrate; a first semiconductor region and a second semiconductor region provided in the semiconductor substrate; a plurality of third semiconductor regions selectively provided in the semiconductor substrate, a plurality of first and second trenches penetrating through the second and third semiconductor regions and reaching the first semiconductor region; a plurality of gate electrodes respectively provided in the first trenches; a plurality of conductive films respectively embedded in the second trenches, junction interfaces between the first semiconductor region and the conductive films forming a plurality of Schottky barriers; a first electrode and a second electrode; and a plurality of Schottky barrier diodes that respectively include the plurality of Schottky barriers. Each conductive film includes first and second metal films, the second metal film being closer to a center of the respective second trench and having a lower electrical resistivity than the first metal film.

公开(公告)号：US11715640B2

公开(公告)日：2023-08-01

申请号：US17213723

申请日：2021-03-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Szu-Ping Tung ,  Chun-Kai Chen ,  Tze-Liang Lee ,  Yi-Nien Su

IPC分类号： H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L21/3081 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/311 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/31144

摘要： In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

公开(公告)号：US20230238305A1

公开(公告)日：2023-07-27

申请号：US18157033

申请日：2023-01-19

申请人： XINTEC INC.

发明人： Ching-Ting PENG ,  Sheng-Hsiang FU ,  Hsin-Yi CHEN

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/784 ,  H01L21/304 ,  H01L21/308 ,  H01L21/683

CPC分类号： H01L23/481 ,  H01L24/05 ,  H01L24/03 ,  H01L24/32 ,  H01L21/784 ,  H01L21/304 ,  H01L21/3086 ,  H01L21/6835 ,  H01L2224/02381 ,  H01L2224/02317 ,  H01L2224/05073 ,  H01L2224/05575 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05567 ,  H01L2224/32225 ,  H01L2221/68372

摘要： A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

公开(公告)号：US11710691B2

公开(公告)日：2023-07-25

申请号：US17082512

申请日：2020-10-28

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Francis J. Carney ,  Jefferson W. Hall ,  Michael J. Seddon

IPC分类号： H01L23/498 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/78 ,  H01L21/67 ,  H01L21/66 ,  H01L21/56 ,  H01L23/31 ,  H02M3/158 ,  H01L23/482 ,  H01L25/065 ,  H01L25/00 ,  H01L23/544 ,  H01L21/02 ,  H01L21/304 ,  H01L21/308 ,  H01L27/146 ,  H01L21/288 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L29/08 ,  H01L23/15 ,  H01L23/367 ,  H01L23/14

CPC分类号： H01L23/49827 ,  H01L21/02035 ,  H01L21/288 ,  H01L21/304 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/486 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/26 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/4822 ,  H01L23/4951 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/562 ,  H01L24/00 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/14 ,  H01L27/14683 ,  H01L29/0847 ,  H02M3/158 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49816 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2221/68327 ,  H01L2223/5446 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3511 ,  H01L2924/3511 ,  H01L2924/00

摘要： A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

公开(公告)号：US20230232610A1

公开(公告)日：2023-07-20

申请号：US18125859

申请日：2023-03-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： MIN-CHUNG CHENG

IPC分类号： H10B12/00 ,  H01L21/308 ,  H01L21/3065

CPC分类号： H10B12/053 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/3081 ,  H10B12/34

摘要： The present disclosure provides a semiconductor structure having a fin structure. The semiconductor includes a substrate defined with an active region. A first gate structure is disposed in the active region and includes a dielectric material. A second gate structure is disposed in the active region and includes the dielectric material. A fin structure having a first top surface is arranged to alternate with the first gate structure and the second gate structure. The first gate structure has a second top surface and the second gate structure has a third top surface. The second top surface and the third top surface are lower than the first top surface.

公开(公告)号：US20230230883A1

公开(公告)日：2023-07-20

申请号：US17858036

申请日：2022-07-05

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hiroshi Yoshida

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/321

CPC分类号： H01L21/823462 ,  H01L21/0332 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3212 ,  H01L21/31053 ,  H01L21/823481 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

公开(公告)号：US11705509B2

公开(公告)日：2023-07-18

申请号：US16992067

申请日：2020-08-12

申请人： Murata Manufacturing Co., Ltd.

发明人： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC分类号： H01L29/737 ,  H01L29/205 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H03F3/21

CPC分类号： H01L29/7371 ,  H01L21/28575 ,  H01L21/308 ,  H01L21/30612 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/66318 ,  H01L29/0817 ,  H01L29/0826 ,  H03F3/21

摘要： A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US11705451B2

公开(公告)日：2023-07-18

申请号：US17394991

申请日：2021-08-05

申请人： Samsung Electronics Co., Ltd.

发明人： Inwon Park ,  Bosoon Kim ,  Jongsoon Park

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L27/02 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L27/085 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L27/0207

摘要： A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.