Electrical Contactor, Especially Wafer Level Contactor, Using Fluid Pressure
    122.
    发明申请
    Electrical Contactor, Especially Wafer Level Contactor, Using Fluid Pressure 失效
    电接触器,特别是晶圆接触器,使用流体压力

    公开(公告)号:US20090072848A1

    公开(公告)日:2009-03-19

    申请号:US12277653

    申请日:2008-11-25

    CPC classification number: G01R31/2887 G01R1/0735 G01R31/2886

    Abstract: An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements and corresponding second contact elements on the device under test. In a further embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact terminals and a semiconductor substrate which includes a plurality of second contact terminals. A plurality of freestanding, resilient contact elements, in one embodiment, are mechanically coupled to one of the flexible wiring layers or the semiconductor substrate and make electrical contacts between corresponding ones of the first contact terminals and the second contact terminals. In another embodiment, a method of making electrical interconnections includes joining a flexible wiring layer and a substrate together in proximity and causing a pressure differential between a first side and a second side of the flexible wiring layer. The pressure differential deforms the flexible wiring layer and causes a plurality of first contact terminals on the flexible wiring layer to electrically connect with a corresponding plurality of second contact terminals on the substrate.

    Abstract translation: 电互连组件和用于制造电互连组件的方法。 在一个实施例中,互连组件包括具有多个第一接触元件和耦合到柔性布线层的流体容纳结构的柔性布线层。 当容纳在流体容纳结构中时,流体将柔性布线层压向被测器件,以在被测器件上的第一接触元件和对应的第二接触元件之间形成电互连。 在另一实施例中,互连组件包括具有多个第一接触端子的柔性布线层和包括多个第二接触端子的半导体衬底。 在一个实施例中,多个独立的弹性接触元件机械耦合到柔性布线层或半导体衬底中的一个,并且在对应的第一接触端子和第二接触端子之间形成电接触。 在另一个实施例中,制造电互连的方法包括将柔性布线层和基板接合在一起并在柔性布线层的第一侧和第二侧之间形成压差。 压差使柔性布线层变形,使柔性布线层上的多个第一接触端子与基板上的对应的多个第二接触端子电连接。

    Electrical contactor, especially wafer level contactor, using fluid pressure
    124.
    发明授权
    Electrical contactor, especially wafer level contactor, using fluid pressure 失效
    电气接触器,特别是晶圆级接触器,使用流体压力

    公开(公告)号:US07455540B2

    公开(公告)日:2008-11-25

    申请号:US11691369

    申请日:2007-03-26

    CPC classification number: G01R31/2887 G01R1/0735 G01R31/2886

    Abstract: An interconnect assembly can include a semiconductor device that is to be tested, and the semiconductor device can include compliant, elongate contact structures that provide an electrical interface to the semiconductor device. The interconnect assembly can also include a flexible wiring substrate, which can have electrical connections to a semiconductor tester. The flexible wiring substrate can also include electrically conductive contact features located on the substrate in a pattern that corresponds to the elongate contact structures of the semiconductor device to be tested. The flexible wiring substrate can also include wiring that interconnects the probes to the electrical connections to the semiconductor tester. The semiconductor device can be located such that some of the elongate contact structures of the semiconductor device are near some of the conductive contact features of the substrate.

    Abstract translation: 互连组件可以包括待测试的半导体器件,并且半导体器件可以包括提供到半导体器件的电接口的顺应的细长接触结构。 互连组件还可以包括柔性布线基板,其可以具有到半导体测试器的电连接。 柔性布线基板还可以包括位于基板上的导电接触特征,其图形对应于要测试的半导体器件的细长接触结构。 柔性布线基板还可以包括将探针互连到与半导体测试器的电连接的布线。 半导体器件可以被定位成使得半导体器件的一些细长接触结构靠近衬底的一些导电接触特征。

    WAFER LEVEL INTERPOSER
    125.
    发明申请

    公开(公告)号:US20080265922A1

    公开(公告)日:2008-10-30

    申请号:US12169538

    申请日:2008-07-08

    CPC classification number: G01R1/07378 G01R1/07307 H01L2924/0002 H01L2924/00

    Abstract: Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements.

    Abstract translation: 双面插入器组件及其形成和使用方法。 在本发明的一个示例中,插入器包括具有第一表面和与所述第一表面相对的第二表面的基板,设置在所述基板的所述第一侧上的第一多个接触元件和设置在所述第一表面上的第二多个接触元件 所述基板的所述第二表面,其中所述插入件经由所述第一和第二多个接触元件连接电子器件。

    High density planar electrical interface
    126.
    发明授权
    High density planar electrical interface 失效
    高密度平面电接口

    公开(公告)号:US07335057B2

    公开(公告)日:2008-02-26

    申请号:US11532801

    申请日:2006-09-18

    CPC classification number: G01R1/0466 H01R13/025 H01R13/40 H01R2201/20

    Abstract: An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.

    Abstract translation: 一种包括具有多个通孔的基板和包括电线和/或同轴电缆的多根电缆的设备,其延伸穿过基板的多个通孔中的相应的通孔。 每个电缆包括导体并围绕基板的表面终止,使得多个电缆中的相应电缆的导体平面对准并且可用于电接触。 一种系统,包括延伸穿过所述界面的主体的多个通孔中的相应一个的电缆接口; 互连部件,其包括与所述多根电缆中的相应导体对准的第一多个接触点以及与要测试的设备的相应接触点对准的第二多个接触点。 而且,一种通过电子部件之间的多根电缆的导线路由信号的方法。

    Predictive, adaptive power supply for an integrated circuit under test
    129.
    发明授权
    Predictive, adaptive power supply for an integrated circuit under test 有权
    用于被测集成电路的预测,自适应电源

    公开(公告)号:US07245120B2

    公开(公告)日:2007-07-17

    申请号:US11237092

    申请日:2005-09-27

    Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

    Abstract translation: 主电源将电流通过路径阻抗提供给被测集成电路器件(DUT)的电源端子。 在测试期间,DUT对电源输入端的电流需求暂时增加了在测试期间施加到DUT的时钟信号的随后边缘,作为IC开关中的晶体管响应于时钟信号的边缘。 为了限制电源输入端子的电压变化(噪声),辅助电源为电源输入端子提供额外的电流脉冲,以满足在时钟信号的每个周期期间增加的需求。 电流脉冲的大小是在该时钟周期期间电流需求的预测增加以及由反馈电路控制的适配信号的大小的函数,以设置用于限制在DUT的功率输入端产生的电压变化。

    Mechanically reconfigurable vertical tester interface for IC probing
    130.
    发明授权
    Mechanically reconfigurable vertical tester interface for IC probing 失效
    用于IC探测的机械可重构垂直测试仪接口

    公开(公告)号:US07230437B2

    公开(公告)日:2007-06-12

    申请号:US10868425

    申请日:2004-06-15

    CPC classification number: G01R31/2889 G01R1/0416 G01R1/07307

    Abstract: A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, and unpluggable using pins, enabling movement over a range of positions.

    Abstract translation: 晶片测试组件包括多个探针头基底,其布置成瓦片,其中连接器连接到一侧,探针支撑在相对侧上。 在一个实施例中,柔性电缆连接器将探头头瓦片上的连接器直接连接到测试头,而在另一实施例中,柔性电缆将探头头瓦片连接到PCB,从而为测试头连接器提供水平布线。 在一个实施例中,调平销提供连接到附接到瓦片的保持元件以提供施加推挽平整力的简化支撑结构。 测试头连接器接口框架能够重新布置测试头和探针卡之间的连接器,以提供完整的晶片接触或部分晶片接触。 测试头连接器通过在轨道上滑动来重新布置,并且使用引脚可拔出,使得能够在一定范围的位置上移动。

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