公开(公告)号：US20180204820A1

公开(公告)日：2018-07-19

申请号：US15408263

申请日：2017-01-17

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Se Young Yang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/768 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L25/0657 ,  G11C11/005 ,  G11C14/0018 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311

Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.

公开(公告)号：US09935076B1

公开(公告)日：2018-04-03

申请号：US15264087

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L21/77 ,  H01L21/66

CPC classification number: H01L21/77 ,  H01L24/17 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US09748227B2

公开(公告)日：2017-08-29

申请号：US15057588

申请日：2016-03-01

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/08 ,  H01L27/06 ,  H01L21/77 ,  H01L49/02

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

公开(公告)号：US09633974B2

公开(公告)日：2017-04-25

申请号：US14638925

申请日：2015-03-04

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu ,  Kwan-Yu Lai ,  Mengzhi Pang ,  Chonghua Zhong ,  Se Young Yang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

公开(公告)号：US09624093B2

公开(公告)日：2017-04-18

申请号：US14543468

申请日：2014-11-17

Applicant: Apple Inc.

Inventor： Tongbi Jiang ,  Jun Zhai

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0048 ,  B81B2207/012 ,  B81C1/00325 ,  B81C2203/0154

Abstract: MEMS packages and modules are described. In an embodiment, a module includes a package mounted within an opening in a module board. The package includes a flexible wiring board mounted to a back surface of the module board and spanning across the opening in the module board. A die is mounted on the flexible wiring board and is encapsulated within an overmold. An air gap exists laterally between the overmold and side surface of the opening in the module board.

公开(公告)号：US20170025380A1

公开(公告)日：2017-01-26

申请号：US14918189

申请日：2015-10-20

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L25/00 ,  H01L21/311 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2224/83005

Abstract: Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

Abstract translation: 描述了半导体封装和扇出芯片堆叠过程。 在一个实施例中，封装包括第一级管芯和从第一级管芯的前侧突出的一排导电柱。 第二级有源管芯附接到第一级管芯的前侧，并且再分配层（RDL）形成在与该行导电柱和第二级有源管芯的前侧电接触。

公开(公告)号：US20170018497A1

公开(公告)日：2017-01-19

申请号：US15018951

申请日：2016-02-09

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Kunzhong Hu

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/16 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102 ,  H01L2224/81

Abstract: In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit.

Abstract translation: 在一些实施例中，方法和/或系统可以包括集成电路。 集成电路可以包括半导体管芯。 集成电路可以包括多个布线层。 可以在多个布线层内形成至少一个金属 - 绝缘体金属（MIM）电容器。 集成电路可以包括电路。 电路可以包括至少一个电感器和电压调节器，其与MIM电容器一起形成用于半导体管芯的电压调节器。 电路可以在多层中的MIM电容器的至少一部分基本上被耦合。 电路可以通过多个布线层电耦合到电容器。 集成电路可以包括多个电连接器，多个电连接器在与电路占据的第二表面的区域分开的点处耦合到第二表面。

公开(公告)号：US20160278671A1

公开(公告)日：2016-09-29

申请号：US15181229

申请日：2016-06-13

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Jun Zhai

IPC: A61B5/1172 ,  G06K9/00 ,  A61B5/053

CPC classification number: A61B5/1172 ,  A61B5/053 ,  A61B2562/0214 ,  A61B2562/182 ,  G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

Abstract translation: 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US20160260695A1

公开(公告)日：2016-09-08

申请号：US14637109

申请日：2015-03-03

Applicant: Apple Inc.

Inventor： Chih-Ming Chung ,  Jun Zhai ,  Yizhang Yang

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/14 ,  H01L24/19 ,  H01L24/32 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL），第一和第二RDL之间的堆叠管芯，以及在RDL之间延伸的导电柱。 模塑料可以将堆叠的管芯和导电柱塞在第一和第二RDL之间。

公开(公告)号：US20160218094A1

公开(公告)日：2016-07-28

申请号：US15087200

申请日：2016-03-31

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。