公开(公告)号：US09653429B2

公开(公告)日：2017-05-16

申请号：US14855397

申请日：2015-09-16

申请人： ChipMOS Technologies Inc. ,  ChipMOS Technologies (Bermuda) Ltd.

发明人： Shih-Wen Chou

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/83

摘要： A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads in the chip connecting zone and a plurality of first outer pads outside of the chip connecting zone. The blocking structure is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone and has a plurality of second pads. The second conductive bumps are disposed between the first inner pads and the second pads. The underfill is disposed between the first chip and the second chip so as to cover the second conductive bumps.

公开(公告)号：US09159685B2

公开(公告)日：2015-10-13

申请号：US14494026

申请日：2014-09-23

申请人： CHIPMOS TECHNOLOGIES INC.

发明人： Geng-Shin Shen ,  Chung-Pang Chi

IPC分类号： H01L21/44 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/034 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a semiconductor substrate, a pad, a passivation layer and a patterned insulating layer. The patterned insulating layer is disposed on the passivation layer and partially and directly covers the first opening of the pad to expose a second opening. The conductive structure comprises an under bump metal (UBM) layer and a conductive bump. The UBM layer is disposed in the second opening defined by the patterned insulating layer and is electrically connected to the pad. The conductive bump is disposed on the UBM layer and is electrically connected to the UBM layer. The upper surface of the conductive bump is greater than the upper surface of the patterned insulating layer, while the portion of the conductive bump disposed in the second opening is covered by the UBM layer.

摘要翻译： 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括半导体衬底，衬垫，钝化层和图案化绝缘层。 图案化的绝缘层设置在钝化层上，并且部分地并且直接覆盖焊盘的第一开口以露出第二开口。 导电结构包括凹凸金属（UBM）层和导电凸块。 UBM层设置在由图案化的绝缘层限定的第二开口中，并且电连接到焊盘。 导电凸块设置在UBM层上并与UBM层电连接。 导电凸块的上表面大于图案化绝缘层的上表面，而布置在第二开口中的导电凸块的部分被UBM层覆盖。

公开(公告)号：US09087912B2

公开(公告)日：2015-07-21

申请号：US14198493

申请日：2014-03-05

申请人： CHIPMOS TECHNOLOGIES INC

发明人： Tsung Jen Liao

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/10 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1624 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00014

摘要： The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.

摘要翻译： 本公开涉及一种晶片级封装的方法及其封装结构。 该方法包括几个步骤。 在插入件中形成的通孔的厚度小于第一导电柱的长度。 第一导柱设置在通孔的内部。 再分配层设置并与第一导电柱电连接。 在再分配层上设置焊球，以形成晶片级封装结构。

公开(公告)号：US20150076670A1

公开(公告)日：2015-03-19

申请号：US14255973

申请日：2014-04-18

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/31 ,  H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/552 ,  H01L23/433

CPC分类号： H01L23/552 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3737 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a substrate, a chip, a plurality of wires, a film layer, a carrier, and an encapsulant. The substrate has an upper surface and a lower surface. The chip is mounted on the upper surface of the substrate. The wires are electrically connected to the chip and the substrate respectively. The film layer is attached to the substrate and entirely encapsulates the chip and the wires. The carrier is adhered on the film layer. The encapsulant is disposed on the upper surface of the substrate, wherein the encapsulant has an electro-magnetic shielding filler. The encapsulant at least partially encapsulates the carrier and the film layer, and the encapsulant covers the chip and the wires.

摘要翻译： 提供了芯片封装结构及其制造方法。 芯片封装结构包括基板，芯片，多根导线，薄膜层，载体和密封剂。 基板具有上表面和下表面。 芯片安装在基板的上表面上。 电线分别与芯片和基板电连接。 膜层附着在基片上，完全封装芯片和电线。 载体粘附在膜层上。 密封剂设置在基板的上表面上，其中密封剂具有电磁屏蔽填料。 密封剂至少部分地封装载体和膜层，并且密封剂覆盖芯片和电线。

公开(公告)号：US20150061121A1

公开(公告)日：2015-03-05

申请号：US14198493

申请日：2014-03-05

申请人： CHIPMOS TECHNOLOGIES INC

发明人： TSUNG JEN LIAO

IPC分类号： H01L23/00

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/10 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1624 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/244 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/821 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00014

摘要： The present disclosure relates to a method for wafer level packaging and a package structure thereof. The method includes several steps. A through hole is formed in the interposer with a thickness that is less than the length of a first conducting pillar. The first conducting pillar is disposed inside the through hole. A redistribution layer is disposed and electrically connected with the first conducting pillar. A solder ball is disposed on the redistribution layer so as to form a wafer level packaging structure.

摘要翻译： 本公开涉及一种晶片级封装的方法及其封装结构。 该方法包括几个步骤。 在插入件中形成的通孔的厚度小于第一导电柱的长度。 第一导柱设置在通孔的内部。 再分配层设置并与第一导电柱电连接。 在再分配层上设置焊球，以形成晶片级封装结构。

公开(公告)号：US08786109B2

公开(公告)日：2014-07-22

申请号：US13793241

申请日：2013-03-11

申请人： Chipmos Technologies Inc.

发明人： Chung-Pang Chi

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/768 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/061 ,  H01L2224/06163 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/141 ,  H01L2224/14153 ,  H01L2924/381 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A conductive structure for a semiconductor chip and a method for forming the conductive structure are provided. The semiconductor chip comprises a plurality of first pads and second pads. The pad area is defined with a first area, a second area and a third area, wherein the first area is located between the second area and the third area. Each of the first pads and the second pads are interlaced to each other on the first area. The conductive structure comprises a plurality of conductive bumps formed on each of the first pads and the second pads respectively to electrically connect with each of the first pads and the second pads. Each of the conductive bumps has a first bump-width disposed on the first area and a second bump-width disposed on one of the second and third areas in which the first bump-width is shorter than the second bump-width.

摘要翻译： 提供了一种用于半导体芯片的导电结构和用于形成导电结构的方法。 半导体芯片包括多个第一焊盘和第二焊盘。 焊盘区域被限定有第一区域，第二区域和第三区域，其中第一区域位于第二区域和第三区域之间。 第一焊盘和第二焊盘中的每一个在第一区域上彼此交错。 导电结构包括分别形成在每个第一焊盘和第二焊盘上的多个导电凸块，以与第一焊盘和第二焊盘中的每一个电连接。 每个导电凸块具有设置在第一区域上的第一凸起宽度和设置在第一凸起宽度比第二凸起宽度短的第二和第三区域中的一个上的第二凸起宽度。

公开(公告)号：US08786082B2

公开(公告)日：2014-07-22

申请号：US13671202

申请日：2012-11-07

申请人： Chipmos Technologies Inc.

发明人： Geng-Shin Shen

IPC分类号： H01L23/48

CPC分类号： H01L24/14 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05013 ,  H01L2224/05022 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/14104 ,  H01L2224/1412 ,  H01L2224/14153 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

摘要翻译： 提供半导体结构。 半导体结构包括衬底，至少两个焊盘，钝化层，至少两个凸块下金属化（UBM）层和至少两个凸块。 焊盘沿着第一方向在基板上彼此相邻设置。 钝化层覆盖基板和每个焊盘的周边上表面以限定开口。 每个开口限定沿着第二方向的开口凸起。 开口突起彼此相邻设置，但彼此不重叠。 此外，第一方向垂直于第二方向。 UBM层设置在相应的开口上，凸块分别设置在相应的UBM层上。 利用上述布置，本发明的半导体结构的每个凸起的宽度可以被加宽而不受凸点间距的限制。

公开(公告)号：US20140004697A1

公开(公告)日：2014-01-02

申请号：US13534289

申请日：2012-06-27

申请人： GENG SHIN SHEN

发明人： GENG SHIN SHEN

IPC分类号： H01L21/283

CPC分类号： H01L21/4853 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/05552

摘要： The present disclosure is related to a method of providing a die structure for semiconductor packaging. The method includes providing a substrate with a bonding pad; forming a patterned mask layer on the substrate; forming an opening on the mask layer; depositing a conductive layer in the opening; forming a cap layer on the conductive layer, and removing the mask layer. The cap layer forming step allows the contacting area between the cap layer and the conductive layer to be substantially equal to the top surface area of the conductive layer by reflowing solder material prior to the removal of the mask layer.

摘要翻译： 本公开涉及提供用于半导体封装的管芯结构的方法。 该方法包括：提供具有接合焊盘的基板; 在衬底上形成图案化掩模层; 在掩模层上形成开口; 在开口中沉积导电层; 在导电层上形成覆盖层，除去掩模层。 盖层形成步骤允许在去除掩模层之前通过回流焊料材料，覆盖层和导电层之间的接触面积基本上等于导电层的顶表面积。

公开(公告)号：US08564954B2

公开(公告)日：2013-10-22

申请号：US12948964

申请日：2010-11-18

申请人： Tzu Hsin Huang ,  Yu Ting Yang ,  Hung Hsin Liu ,  An Hong Liu ,  Geng Shin Shen ,  Wei David Wang ,  Shih Fu Lee

发明人： Tzu Hsin Huang ,  Yu Ting Yang ,  Hung Hsin Liu ,  An Hong Liu ,  Geng Shin Shen ,  Wei David Wang ,  Shih Fu Lee

IPC分类号： H05K7/20 ,  F28F7/00

CPC分类号： H05K7/205 ,  B82B1/005 ,  B82Y10/00 ,  B82Y30/00 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/525 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K5/0213 ,  Y10S977/932 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A thermally enhanced electronic package comprises a driver chip, an insulator, a flexible carrier, and carbon nanocapsules. The flexible carrier includes a flexible substrate, a wiring layer formed on the substrate, and a resistant overlaying the wiring layer. The driver chip is connected to the wiring layer. The insulator is filled in the gap between the driver chip and the flexible carrier. The carbon nanocapsules are disposed on the driver chip, on the resistant, on the flexible carrier, or in the insulator to enhance heat dissipation of electronic packages.

摘要翻译： 热增强型电子封装包括驱动器芯片，绝缘体，柔性载体和碳纳米胶囊。 柔性载体包括柔性基板，形成在基板上的布线层和覆盖布线层的电阻。 驱动器芯片连接到布线层。 绝缘体填充在驱动器芯片和柔性载体之间的间隙中。 碳纳米胶囊设置在驱动芯片上，电阻上，柔性载体上或绝缘体中，以增强电子封装的散热。

公开(公告)号：US20130248863A1

公开(公告)日：2013-09-26

申请号：US13849294

申请日：2013-03-22

申请人： CHIPMOS TECHNOLOGIES, INC.

发明人： Ying-Tai TANG

IPC分类号： H01L21/66

CPC分类号： H01L22/30 ,  H01L22/32 ,  H01L23/49838 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2924/00012

摘要： A chip packaging substrate includes a flexible substrate, a plurality of test pads, and a plurality of leads, wherein the flexible substrate has a first surface and a second surface, and the first surface has a user area and a test pad area configured thereon. The test pads are arranged in at least three rows within the test pad area. The lead connected to the test pad in the middle row includes a first section extending from the chip to the test pad area and a second section disposed on the second surface, wherein one end of the second section penetrates the flexible substrate to connect with the first section and the other end penetrates the flexible substrate to connect with the test pad, so as to increase the dimensions of the test pads.

摘要翻译： 芯片封装基板包括柔性基板，多个测试焊盘和多个引线，其中柔性基板具有第一表面和第二表面，并且第一表面具有配置在其上的用户区域和测试焊盘区域。 测试垫被布置在测试垫区域内至少三排。 连接到中间行的测试垫的引线包括从芯片延伸到测试焊盘区域的第一部分和设置在第二表面上的第二部分，其中第二部分的一端穿透柔性基板以与第一部分连接 并且另一端穿透柔性基板以与测试垫连接，以便增加测试垫的尺寸。