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    CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS
    144.
    发明申请
    CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS 审中-公开

    公开(公告)号：US20170324208A1

    公开(公告)日：2017-11-09

    申请号：US15659351

    申请日：2017-07-25

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： DARKO R. POPOVIC

    IPC: H01R43/20 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552

    CPC classification number: H01R43/205 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09609 ,  H05K2201/09636

    Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.

    Breakout via system
    145.
    发明授权
    Breakout via system 有权

    公开(公告)号：US09769926B2

    公开(公告)日：2017-09-19

    申请号：US14694759

    申请日：2015-04-23

    Applicant: Dell Products L.P.

    Inventor： Kevin Warren Mundt ,  Sandor Farkas ,  Bhyrav Mutnury

    IPC: H05K1/11 ,  H05K1/02 ,  G06F1/20 ,  G06F1/18

    CPC classification number: H05K1/114 ,  G06F1/185 ,  G06F1/20 ,  H05K1/0222 ,  H05K1/0251 ,  H05K2201/09609 ,  H05K2201/09636

    Abstract: A circuit board includes a board base with a first surface and a second surface that is located opposite the first surface. A plurality of first coupling pads are located on the first surface of the board base. A plurality of second coupling pads are located on the second surface of the board base. The first coupling pads and the second coupling pads define a coupling pad footprint. A breakout via system is included in the board base. The breakout via system includes a plurality of primary signal vias that are located in the board base and outside of the coupling pad footprint, a plurality of first primary signal via connections that extend between the primary signal vias and the plurality of first coupling pads, and a plurality of second primary signal via connections that extend between the primary signal vias and the plurality of second coupling pads.

    CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS
    147.
    发明申请
    CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS 有权
    电气互连中的减速器

    公开(公告)号：US20160205770A1

    公开(公告)日：2016-07-14

    申请号：US14593735

    申请日：2015-01-09

    Applicant: ORACLE INTERNATIONAL CORPORATION

    Inventor： DARKO R. POPOVIC

    IPC: H05K1/02 ,  H01R43/20

    CPC classification number: H01R43/205 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09609 ,  H05K2201/09636

    Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.

    Abstract translation: 实施例通过偏移电气系统中的电互连对来减少电互连之间的串扰，以产生交错的互连图案，通过由受害互连对形成的环路的磁通被有效地消除。 由侵略者互连对产生的磁场矢量可以通过系统中受害对互连对界定的循环界定的表面。 在交错的互连图案中，受害者互连对相对于侵略者互连对偏移，使得在一个方向上通过受害对的循环界限的场矢量基本上通过穿过受害者对的环路 - 相反方向的有界表面，从而最小化侵略者对的磁场对受害者对的影响。 由于串扰与磁通量的变化率成比例，所以减小磁通可以减少串扰。

    Printed wiring board
    148.
    发明授权
    Printed wiring board 有权
    印刷电路板

    公开(公告)号：US09374897B2

    公开(公告)日：2016-06-21

    申请号：US14823519

    申请日：2015-08-11

    Applicant: FANUC Corporation

    Inventor： Makoto Bekke

    IPC: H05K1/11

    CPC classification number: H05K1/115 ,  H05K3/3447 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2203/044

    Abstract: A printed wiring board includes three or more than three through holes. An inner wall of the through hole is covered by conductive coating. Same size leads of an electronic component are inserted into the through holes. The through holes are soldered by dip soldering the printed wiring board in melting solder. The through holes have two or more diameters. The diameter of the through hole having more adjacent through holes is not larger than the diameter of the through hole having less adjacent through holes.

    Abstract translation: 印刷电路板包括三个或三个以上的通孔。 通孔的内壁被导电涂层覆盖。 将电子部件的相同尺寸的引线插入到通孔中。 通孔通过浸焊焊接印刷线路板而熔化焊料来焊接通孔。 通孔具有两个或更多个直径。 具有更多相邻通孔的通孔的直径不大于具有较少相邻通孔的通孔的直径。

    CIRCUIT BOARD VIA CONFIGURATIONS FOR HIGH FREQUENCY SIGNALING
    150.
    发明申请
    CIRCUIT BOARD VIA CONFIGURATIONS FOR HIGH FREQUENCY SIGNALING 有权
    电路板通过高频信号配置

    公开(公告)号：US20150114706A1

    公开(公告)日：2015-04-30

    申请号：US14511397

    申请日：2014-10-10

    Applicant: Curtiss-Wright Controls, Inc.

    Inventor： Michael Rose ,  Robert Sullivan

    IPC: H05K1/02 ,  H05K1/11

    CPC classification number: H05K1/0251 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4038 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/1059

    Abstract: A circuit board comprises a plurality of layers, first and second reference conductive vias extending in a vertical direction through at least a portion of the plurality of layers, first and second signal conductive vias extending in the vertical direction between and spaced apart in a horizontal direction from the first and second reference conductive vias through at least a portion of the plurality of layers, and a dielectric region extending in the vertical direction between the first and second signal conductive vias. An air via extends in the vertical direction through the dielectric region between the first and second signal conductive vias. An anti-pad extends in the horizontal direction between the first and second reference conductive vias and surrounding in the horizontal direction the first and second signal conductive vias, the air via, and the dielectric region.

    Abstract translation: 电路板包括多个层，第一和第二参考导电通孔在垂直方向上延伸穿过多个层的至少一部分，第一和第二信号导电通孔在垂直方向上延伸并且在水平方向间隔开 从所述第一和第二参考导电通孔穿过所述多个层的至少一部分，以及在所述第一和第二信号导电通孔之间沿垂直方向延伸的电介质区域。 空气通道在垂直方向上延伸穿过第一和第二信号导电通孔之间的电介质区域。 反焊盘在第一和第二参考导电通孔之间沿水平方向延伸，并且在水平方向上包围第一和第二信号导电通孔，空气通孔和电介质区域。

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