公开(公告)号：US20240272980A1

公开(公告)日：2024-08-15

申请号：US18444320

申请日：2024-02-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Steven Haukness

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G06F12/0246 ,  G11C29/52

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US20240257863A1

公开(公告)日：2024-08-01

申请号：US18584371

申请日：2024-02-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US12032845B2

公开(公告)日：2024-07-09

申请号：US17505503

申请日：2021-10-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0679

Abstract: A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.

公开(公告)号：US11963299B2

公开(公告)日：2024-04-16

申请号：US17726354

申请日：2022-04-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: G11C7/00 ,  G06F1/18 ,  G06F13/16 ,  G06F13/40 ,  G06F15/78 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US11960418B2

公开(公告)日：2024-04-16

申请号：US17965684

申请日：2022-10-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G11C7/22 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/02

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/02 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US11960344B2

公开(公告)日：2024-04-16

申请号：US18092004

申请日：2022-12-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06 ,  G06F13/16 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/36 ,  G06F2201/88 ,  G11C2207/2254 ,  Y02D10/00

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US20240118837A1

公开(公告)日：2024-04-11

申请号：US18487955

申请日：2023-10-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C29/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US11953981B2

公开(公告)日：2024-04-09

申请号：US18092556

申请日：2023-01-03

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0772 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26 ,  G11C29/44

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US20240111423A1

公开(公告)日：2024-04-04

申请号：US18492296

申请日：2023-10-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F3/06 ,  G06F12/06 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

公开(公告)号：US20240054084A1

公开(公告)日：2024-02-15

申请号：US18239681

申请日：2023-08-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.