公开(公告)号：US20190259704A1

公开(公告)日：2019-08-22

申请号：US16401661

申请日：2019-05-02

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Paik Wen Ong

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/48

Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US20190109122A1

公开(公告)日：2019-04-11

申请号：US15845492

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim ,  Kooi Chi Ooi

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L21/48 ,  H01L23/492 ,  H01L23/538

Abstract: A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

公开(公告)号：US10158339B2

公开(公告)日：2018-12-18

申请号：US14966635

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Wil Choon Song

IPC: H05K5/00 ,  H03H7/38 ,  G06F13/38 ,  G06F17/50 ,  H01P3/08 ,  H05K1/18 ,  H05K3/00 ,  H01P3/02 ,  H05K7/00 ,  H05K7/18 ,  H05K7/14 ,  H05K9/00 ,  H05K1/02

Abstract: Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.

公开(公告)号：US10079158B2

公开(公告)日：2018-09-18

申请号：US14569438

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Jackson Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Kuan-Yu Chen

IPC: H05K7/00 ,  H01P3/08 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H05K1/00 ,  H05K1/11 ,  H01P3/00 ,  H01P3/02 ,  H01P5/02 ,  H05K1/02 ,  H01P3/04

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/10 ,  H01P3/003 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P3/082 ,  H01P5/028 ,  H05K1/0224 ,  H05K1/0242 ,  H05K1/0245 ,  H05K3/462 ,  H05K3/4638 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/1189

Abstract: An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

公开(公告)号：US10036187B2

公开(公告)日：2018-07-31

申请号：US14996568

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Chung Peng Jackson Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/32 ,  E05D11/00 ,  H05K5/02

Abstract: An apparatus is provided including a docking device to accept a computing device, the docking device including a keyboard and a hinge to connect the computing device to the keyboard, the hinge is configured to allow the computing device, when connected to the hinge, to rotate relative to the keyboard in a laptop orientation. The hinge includes a plurality of interlinked parallel hinge segments at least partially enclosed in a flexible covering, and each hinge segment is to rotate about a respective one of a plurality of parallel axes of the hinge.

公开(公告)号：US10000953B2

公开(公告)日：2018-06-19

申请号：US14996568

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Chung Peng Jackson Kong ,  Poh Tat Oh

IPC: E05D3/06 ,  G06F1/16 ,  G06F1/32 ,  E05D11/00 ,  H05K5/02

Abstract: An apparatus is provided including a docking device to accept a computing device, the docking device including a keyboard and a hinge to connect the computing device to the keyboard, the hinge is configured to allow the computing device, when connected to the hinge, to rotate relative to the keyboard in a laptop orientation. The hinge includes a plurality of interlinked parallel hinge segments at least partially enclosed in a flexible covering, and each hinge segment is to rotate about a respective one of a plurality of parallel axes of the hinge.

公开(公告)号：US20180145042A1

公开(公告)日：2018-05-24

申请号：US15359926

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： Min Suet Lim ,  Chin Lee Kuan ,  Eng Huat Goh ,  Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Howe Yin Loo

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816

Abstract: A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors. An integrated circuit package attached to a motherboard using spiral interconnects is shown. Methods of attaching an integrated circuit package to a motherboard using spiral interconnects are shown including air core inductors. Methods of attaching spiral interconnects include using electrically conductive adhesive or solder.

公开(公告)号：US09778688B2

公开(公告)日：2017-10-03

申请号：US14779300

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jiamiao Tang ,  Junfeng Zhao ,  Michael P. Skinner ,  Yong She ,  Jiun Hann Sir ,  Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC: H01L23/48 ,  G06F1/16 ,  H01L23/31 ,  A41B1/00 ,  A41D1/06 ,  A41D1/08 ,  A41F9/00 ,  A43B3/00 ,  A43B7/14 ,  A44C5/00 ,  A44C15/00 ,  F03G5/06 ,  G06F1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H02J1/14 ,  H05K1/18

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/002 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

公开(公告)号：US20170170799A1

公开(公告)日：2017-06-15

申请号：US14966635

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Khang Choong Yong ,  Howard L. Heck ,  Wil Choon Song

IPC: H03H7/38 ,  H05K1/18 ,  G06F17/50 ,  H01P3/08 ,  G06F13/38 ,  H05K3/00 ,  H05K1/02

CPC classification number: H03H7/38 ,  G06F13/382 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/82 ,  H01P3/026 ,  H01P3/08 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/18 ,  H05K3/0005 ,  H05K9/0039 ,  H05K2201/09218 ,  H05K2201/0929 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09681

Abstract: Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.

公开(公告)号：US20160343686A1

公开(公告)日：2016-11-24

申请号：US14775550

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Shanggar Periaman ,  Michael P. Skinner

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  A44B1/00 ,  G06F1/16 ,  H01L25/00 ,  G02C11/00 ,  A45C1/06 ,  B43K29/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0655 ,  A44B1/00 ,  A45C1/06 ,  B43K29/00 ,  G02C11/10 ,  G06F1/163 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15158 ,  H01L2924/15192 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161

Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于小尺寸或可佩戴装置的集成电路（IC）封装技术和配置。 在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧和设置在第一侧和第二侧之间的侧壁的衬底，侧壁限定衬底的周边，以及多个 布置在基板的第一侧和第二侧之间的贯通基板通孔（TSV）以及布置在第一侧上的第一介电层，并且包括电路径特征以将一个或多个管芯的电信号路由在第一 电介质层。 可以描述和/或要求保护其他实施例。