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    STACK MODULE, CARD INCLUDING THE STACK MODULE, AND SYSTEM INCLUDING THE STACK MODULE
    11.
    发明申请
    STACK MODULE, CARD INCLUDING THE STACK MODULE, AND SYSTEM INCLUDING THE STACK MODULE 有权
    堆叠模块，包括堆叠模块的卡和包含堆叠模块的系统

    公开(公告)号：US20080304242A1

    公开(公告)日：2008-12-11

    申请号：US12126313

    申请日：2008-05-23

    Applicant: Seung-Duk BAEK ,  Mitsuo UMEMOTO ,  Kang-Wook LEE

    Inventor： Seung-Duk BAEK ,  Mitsuo UMEMOTO ,  Kang-Wook LEE

    IPC: H05K7/00

    CPC classification number: H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541

    Abstract: Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

    Abstract translation: 提供了通过使用简化的处理以低成本制造的高可靠性堆栈模块，使用堆栈模块的卡和使用堆栈模块的系统。 在堆叠模块中，单元基板相对于彼此层叠，并且每个单元基板包括选择端子。 第一选择线电连接到设置在奇数层的第一单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。 第二选择线电连接到以偶数层布置的第二单元基板的选择端子，通过一些单元基板，并延伸到单元基板的最下面的基板。 选择端子设置在第一选择线和第二选择线之间。

    METHOD OF REMOVING GRAPHITIC AND/OR FLUORINATED ORGANIC LAYERS FROM THE SURFACE OF A CHIP PASSIVATION LAYER HAVING SI-CONTAINING COMPOUNDS
    13.
    发明申请
    METHOD OF REMOVING GRAPHITIC AND/OR FLUORINATED ORGANIC LAYERS FROM THE SURFACE OF A CHIP PASSIVATION LAYER HAVING SI-CONTAINING COMPOUNDS 有权
    从含有SI化合物的芯片钝化层的表面去除玻璃化和/或氟化有机层的方法

    公开(公告)号：US20080207002A1

    公开(公告)日：2008-08-28

    申请号：US11679247

    申请日：2007-02-27

    Applicant: Kang-Wook Lee

    Inventor： Kang-Wook Lee

    IPC: H01L21/302

    CPC classification number: H01L21/02082

    Abstract: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.

    Abstract translation: 一种用于从芯片钝化层表面去除不期望的污染物而不在钝化层上产生SiO 2颗粒的方法，其中不需要的污染物包括石墨层和氟化层。 使用具有优化等离子体参数的N 2等离子体可以通过蚀刻石墨和氟化有机层来去除。 N 2等离子体处理的最佳条件是在100-200W的范围内使用相对较低的功率和在N 2 范围500-750 mTorr。

    Wafer-level electronic modules with integral connector contacts
    16.
    发明授权
    Wafer-level electronic modules with integral connector contacts 失效
    具有集成连接器触点的晶圆级电子模块

    公开(公告)号：US07307340B2

    公开(公告)日：2007-12-11

    申请号：US10824111

    申请日：2004-04-14

    Applicant: Seung Duk Baek ,  Dong Hyeon Jang ,  Gu Sung Kim ,  Kang Wook Lee ,  Jae Sik Chung

    Inventor： Seung Duk Baek ,  Dong Hyeon Jang ,  Gu Sung Kim ,  Kang Wook Lee ,  Jae Sik Chung

    IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/34 ,  H01L25/10

    CPC classification number: H01L23/5228 ,  H01L23/367 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/525 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An electronic module comprises a monolithic microelectronic substrate including at least one integrated circuit die, e.g., a plurality of unseparated memory dice or a mixture of different types of integrated circuit dice. The monolithic substrate further includes a redistribution structure disposed on the at least one integrated circuit die and providing a connector contact coupled to the at least one integrated circuit die. For example, the connector contact may be configured as edge connector contact for the module. The redistribution structure may be configured to provide a passive electronic device, e.g., an inductor, capacitor and/or resistor, electrically coupled to the at least one integrated circuit die and/or the redistribution structure may comprise at least one conductive layer configured to provide electrical connection to a contact pad of an electronic device mounted on the substrate. Methods of fabricating electronic modules are also discussed.

    Abstract translation: 电子模块包括单片微电子衬底，其包括至少一个集成电路管芯，例如多个未分离的存储器管芯或不同类型的集成电路管芯的混合。 整体式衬底还包括设置在至少一个集成电路管芯上的再分配结构，并提供耦合到至少一个集成电路管芯的连接器接头。 例如，连接器触点可以被配置为模块的边缘连接器触点。 再分配结构可以被配置为提供电耦合到至少一个集成电路管芯的无源电子器件，例如电感器，电容器和/或电阻器，和/或再分配结构可以包括至少一个导电层，其被配置为提供 电连接到安装在基板上的电子设备的接触焊盘。 还讨论了制造电子模块的方法。

    Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
    20.
    发明授权
    Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures 有权
    多孔低k电介质互连结构的韧性，粘附性和光滑的金属线

    公开(公告)号：US06783862B2

    公开(公告)日：2004-08-31

    申请号：US10290682

    申请日：2002-11-08

    Applicant: Jeffrey C Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S Tyberg

    Inventor： Jeffrey C Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S Tyberg

    IPC: B32B904

    CPC classification number: H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

    Abstract: A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

    Abstract translation: 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

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