公开(公告)号：US06794282B2

公开(公告)日：2004-09-21

申请号：US10305063

申请日：2002-11-27

Applicant: Thomas Goebel ,  Werner Robl ,  Rajeev Malik ,  Mihel Seitz

Inventor： Thomas Goebel ,  Werner Robl ,  Rajeev Malik ,  Mihel Seitz

IPC: H01L2144

CPC classification number: H01L27/10888 ,  H01L21/76882

Abstract: A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.

Abstract translation: 形成半导体器件的方法包括提供包括形成在其上的导体的半导体器件。 在导体上形成电介质层，并且通过去除电介质层的一部分以露出导体的至少一部分，在电介质层中形成凹陷。 沿着电介质层的侧壁并在导体的暴露部分之上沉积在电介质的顶表面上的第一层铝，而不改变半导体器件的温度。 在大于约300℃的温度下，在第一层铝上沉积第二层铝。第三层铝沉积在第二层铝上，以便完全填充介电层中的凹槽。 第三层铝在大于约300℃的温度下缓慢沉积

公开(公告)号：US06720212B2

公开(公告)日：2004-04-13

申请号：US10098840

申请日：2002-03-14

Applicant: Werner Robl ,  Thomas Goebel ,  Axel Christoph Brintzinger ,  Gerald Friese

Inventor： Werner Robl ,  Thomas Goebel ,  Axel Christoph Brintzinger ,  Gerald Friese

IPC: H01L2182

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

Abstract translation: 公开了一种球栅阵列封装的方法，包括以下步骤：提供其上具有金属导体的半导体管芯，用绝缘层覆盖所述金属导体，蚀刻穿过所述绝缘层，以便向所述金属导体提供一个或多个开口 沉积柔性材料层，蚀刻穿过所述柔性材料层，以便向所述金属导体提供一个或多个开口;沉积基本上均匀的导电层;图案化所述导电层，以将所述金属导体中的至少一个导入电 与一个或多个焊盘接触，每个所述焊盘包括设置在所述柔性材料上的所述导电层的一部分，以及设置在所述焊盘上的焊球。 还公开了由该方法制成的装置。

公开(公告)号：US20130278372A1

公开(公告)日：2013-10-24

申请号：US13452075

申请日：2012-04-20

Applicant: Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Werner Robl

Inventor： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Werner Robl

IPC: H01F5/00

CPC classification number: H01L28/10 ,  H01F27/2804 ,  H01F2017/0086 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.

Abstract translation: 半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。 导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。 导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。 导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

公开(公告)号：US20130147047A1

公开(公告)日：2013-06-13

申请号：US13315642

申请日：2011-12-09

Applicant: Thomas Detzel ,  Johann Gross ,  Robert Illing ,  Maximilian Krug ,  Sven Gustav Lanzerstorfer ,  Michael Nelhiebel ,  Werner Robl ,  Michael Rogalli ,  Stefan Woehlert

Inventor： Thomas Detzel ,  Johann Gross ,  Robert Illing ,  Maximilian Krug ,  Sven Gustav Lanzerstorfer ,  Michael Nelhiebel ,  Werner Robl ,  Michael Rogalli ,  Stefan Woehlert

IPC: H01L23/48 ,  H01L21/28

CPC classification number: H01L23/3735 ,  H01L21/2885 ,  H01L21/4882 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.

Abstract translation: 集成电路包括在基底元件上的基底元件和铜元件，铜元件具有至少5μm的厚度，并且平均晶粒尺寸与厚度之比小于0.7。

公开(公告)号：US06734097B2

公开(公告)日：2004-05-11

申请号：US09965094

申请日：2001-09-28

Applicant: Roy C. Iggulden ,  Padraic Shafer ,  Werner Robl ,  Kwong Hon Wong

Inventor： Roy C. Iggulden ,  Padraic Shafer ,  Werner Robl ,  Kwong Hon Wong

IPC: H01L214763

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.

Abstract translation: 一种用衬垫填充镶嵌结构的方法，其特征在于改进的阻力和阻力扩展以及足够的粘合性，其包括：由衬垫涂覆的给定镶嵌结构，其有目的地为上述结构提供差的步骤覆盖，随后进行CVD W沉积， 其次是金属隔离技术。

公开(公告)号：US09425146B2

公开(公告)日：2016-08-23

申请号：US12891865

申请日：2010-09-28

Applicant: Thomas Fischer ,  Juergen Foerster ,  Werner Robl ,  Andreas Stueckjuergen

Inventor： Thomas Fischer ,  Juergen Foerster ,  Werner Robl ,  Andreas Stueckjuergen

IPC: H01L23/532 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/535 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1078 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Abstract translation: 一个或多个实施例涉及制造半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成分离层; 在分离层上形成导电层; 并湿式蚀刻导电层。

公开(公告)号：US09418937B2

公开(公告)日：2016-08-16

申请号：US13315642

申请日：2011-12-09

Applicant: Thomas Detzel ,  Johann Gross ,  Robert Illing ,  Maximilian Krug ,  Sven Gustav Lanzerstorfer ,  Michael Nelhiebel ,  Werner Robl ,  Michael Rogalli ,  Stefan Woehlert

Inventor： Thomas Detzel ,  Johann Gross ,  Robert Illing ,  Maximilian Krug ,  Sven Gustav Lanzerstorfer ,  Michael Nelhiebel ,  Werner Robl ,  Michael Rogalli ,  Stefan Woehlert

IPC: H01L23/52 ,  H01L23/532 ,  H01L21/288

CPC classification number: H01L23/3735 ,  H01L21/2885 ,  H01L21/4882 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of less than 0.7.

Abstract translation: 集成电路包括在基底元件上的基底元件和铜元件，铜元素的厚度至少为5μm，平均晶粒尺寸与厚度之比小于0.7。

公开(公告)号：US20120080791A1

公开(公告)日：2012-04-05

申请号：US12894190

申请日：2010-09-30

Applicant: Hans-Joachim BARTH ,  Gottfried BEER ,  Joern PLAGMANN ,  Jens POHL ,  Werner ROBL ,  Rainer STEINER ,  Mathias VAUPEL

Inventor： Hans-Joachim BARTH ,  Gottfried BEER ,  Joern PLAGMANN ,  Jens POHL ,  Werner ROBL ,  Rainer STEINER ,  Mathias VAUPEL

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.

Abstract translation: 一个或多个实施例涉及一种形成电子设备的方法，包括：提供工件; 在工件上形成第一阻挡层; 在所述第一阻挡层上形成中间导电层; 在所述中间导电层上形成第二阻挡层; 在所述第二阻挡层上形成种子层; 去除种子层的一部分以留下种子层的剩余部分并暴露第二阻挡层的一部分; 并在种子层的剩余部分上电镀填充层。

公开(公告)号：US20120074574A1

公开(公告)日：2012-03-29

申请号：US12893009

申请日：2010-09-29

Applicant: Hans-Joachim BARTH ,  Gottfried BEER ,  Joern PLAGMANN ,  Jens POHL ,  Werner ROBL ,  Rainer STEINER ,  Mathias VAUPEL

Inventor： Hans-Joachim BARTH ,  Gottfried BEER ,  Joern PLAGMANN ,  Jens POHL ,  Werner ROBL ,  Rainer STEINER ,  Mathias VAUPEL

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.

Abstract translation: 一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。

公开(公告)号：US08072071B2

公开(公告)日：2011-12-06

申请号：US12389103

申请日：2009-02-19

Applicant: Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

Inventor： Rainer Steiner ,  Jens Pohl ,  Werner Robl ,  Markus Brunnbauer ,  Gottfried Beer

IPC: H01L23/498

CPC classification number: H01L23/528 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05006 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05546 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Abstract translation: 半导体器件包括芯片，其包括接触元件，芯片上方的结构化介电层以及耦合到接触元件的导电元件。 导电元件包括​​嵌入结构化电介质层中的第一部分，与第一部分至少部分间隔开并嵌入结构化介电层的第二部分，以及接触结构化介电层顶部并至少延伸的第三部分 垂直于第一部分和第二部分。