公开(公告)号：US08716830B2

公开(公告)日：2014-05-06

申请号：US13304167

申请日：2011-11-23

申请人： Anindya Poddar ,  Luu T. Nguyen

发明人： Anindya Poddar ,  Luu T. Nguyen

IPC分类号： H01L21/70

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/4005 ,  H01L2224/40106 ,  H01L2224/40108 ,  H01L2224/40225 ,  H01L2224/40245 ,  H01L2224/40479 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.

摘要翻译： 在本发明的一个方面中，将描述集成电路封装。 集成电路封装包括至少两个与基板连接的集成电路。 集成电路和基板至少部分地封装在模制材料中。 存在部分延伸穿过模制材料并且被布置成在集成电路之间形成热障碍物的凹槽或气隙。

公开(公告)号：US20130127044A1

公开(公告)日：2013-05-23

申请号：US13303073

申请日：2011-11-22

申请人： Anindya Poddar ,  Tao Feng ,  Will K. Wong

发明人： Anindya Poddar ,  Tao Feng ,  Will K. Wong

IPC分类号： H01L23/488 ,  H01L21/78

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/157 ,  H01L2924/15724 ,  H01L2924/1579 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A variety of improved approaches for packaging integrated circuits are described. In one described approach, a multiplicity of die cavities are formed in a plastic carrier. In some preferred embodiments, the die cavities are formed by laser ablation. A multiplicity of dice are placed on the carrier, with each die being placed in an associated die cavity. Each of the dice preferably has a multiplicity of I/O bumps formed thereon. An encapsulant is applied over the carrier to form an encapsulant layer that covers the dice and fills portions of the cavities that are not occupied by the dice. In some preferred embodiments, the encapsulant is an epoxy material applied by screen printing and the dice are not physically attached to the carrier prior to the application of the encapsulant. In these embodiments, the epoxy encapsulant serves to secure the dice to the carrier.

摘要翻译： 描述了用于封装集成电路的各种改进方法。 在一种所描述的方法中，在塑料载体中形成多个模腔。 在一些优选实施例中，模腔通过激光烧蚀形成。 将多个骰子放置在载体上，每个模具被放置在相关的模腔中。 每个骰子优选地具有形成在其上的多个I / O凸块。 将密封剂施加在载体上以形成覆盖骰子并填充未被骰子占据的空腔的部分的密封剂层。 在一些优选的实施方案中，密封剂是通过丝网印刷施加的环氧材料，并且在施加密封剂之前，骰子不物理附着到载体上。 在这些实施例中，环氧树脂密封剂用于将骰子固定到载体上。

公开(公告)号：US08101470B2

公开(公告)日：2012-01-24

申请号：US12571202

申请日：2009-09-30

申请人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

发明人： Anindya Poddar ,  Nghia Thuc Tu ,  Jaime Bayan ,  Will Wong ,  David Chin

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/568 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

摘要： The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

摘要翻译： 本发明涉及使用薄箔在集成电路封装中形成电互连的方法和布置。 本发明的一个实施例涉及将多个骰子附接到箔片载体结构。 箔载体结构由结合到载体的薄箔制成。 然后将模具和至少一部分金属箔用模制材料包封。 移除载体，留下模制的箔结构。 使用光刻技术对暴露的箔进行图案化和蚀刻，以在箔中限定多个器件区域。 每个设备区域包括多条导线。 之后，导电线的一部分被电介质材料覆盖，并且其它部分被暴露以在器件区域中限定多个接合焊盘。 模制的箔结构可以被单个化以形成多个集成电路封装。

公开(公告)号：US07838974B2

公开(公告)日：2010-11-23

申请号：US12167163

申请日：2008-07-02

申请人： Anindya Poddar ,  Lianxi Shen

发明人： Anindya Poddar ,  Lianxi Shen

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/27013 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface of the die attach pad.

摘要翻译： 本发明的具体实施例提供了一种适用于封装IC芯片的引线框，IC芯片能够使芯片内和其周围的应力减小，管芯附着材料，管芯附着垫和模具接口。 更具体地，描述了包括在管芯附接垫的顶表面的选定区域中的凹槽的各种引线框架。

公开(公告)号：US07667304B2

公开(公告)日：2010-02-23

申请号：US12110991

申请日：2008-04-28

申请人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

发明人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

IPC分类号： H01L23/495 ,  H01L21/44

CPC分类号： H01L21/4821 ,  H01L21/6835 ,  H01L23/49579 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.

摘要翻译： 公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。 一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。 然后将nanoink固化以除去液体内容物。 剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。 相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个单独的器件阵列包括多个电互连图案，每个均包括安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关联的电互连图案的模制帽。 模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

公开(公告)号：US20090267216A1

公开(公告)日：2009-10-29

申请号：US12110991

申请日：2008-04-28

申请人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

发明人： Randall L. Walberg ,  Luu T. Nguyen ,  Anindya Poddar

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/4821 ,  H01L21/6835 ,  H01L23/49579 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2924/14 ,  H01L2924/00

摘要： Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays.

摘要翻译： 公开了用于集成电路装置的用于喷墨印刷电互连图案的引线框架的装置和方法。 一种用于包装的装置包括适于高温处理的薄基板，以及使用金属纳米接头喷墨印刷到薄基板上的连接焊盘和接触区域。 然后将nanoink固化以除去液体内容物。 剩余的金属引线框架或电互连图案具有约10至50微米或更小的基本一致的厚度。 相关联的面板组件包括导电衬底面板，该导电衬底面板具有多个单独的器件阵列，每个器件阵列包括多个电互连图案，每个电连接图案，安装在导电衬底面板上的多个集成电路器件，以及封装集成电路器件和相关电气互连图案的模制帽。 模制帽在每个分离的装置阵列上具有基本均匀的厚度，并且延伸到分离的装置阵列之间的空间中。

公开(公告)号：US07385297B1

公开(公告)日：2008-06-10

申请号：US11274903

申请日：2005-11-14

申请人： Vijaylaxmi Gumaste ,  Anindya Poddar

发明人： Vijaylaxmi Gumaste ,  Anindya Poddar

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015

摘要： An under bond pad structure is described for integrated circuit dice are that have active circuits located below at least some of the bond pads. The metallization layers interconnection structures within the die are arranged so that electrically conductive vias do not extend between the bond pads and any underlying metallization layer in a region that overlies an active circuit. In some embodiments, no conductive vias are provided between any of the metallization layers in regions that underlie the bond pads and overlie an active circuit. The described arrangements significantly improve the resistance to cracking in the dielectric layers beneath the bond pad (and particularly the topmost intermediate dielectric layer) when wire bonding is used to electrically connect such dice within a package.

摘要翻译： 对于具有位于至少一些接合焊盘下方的有源电路的集成电路芯片，描述了接合焊盘结构。 管芯内的金属化层互连结构被布置成使得导电通孔不会在覆盖有源电路的区域中的接合焊盘和任何下面的金属化层之间延伸。 在一些实施例中，在位于接合焊盘之下的区域中的任何金属化层之间没有提供导电通孔并覆盖有源电路。 当引线接合用于将这种骰子电连接在封装内时，所描述的布置显着地改善了接合焊盘（特别是最上面的中间介电层）下方的电介质层的抗开裂性。

公开(公告)号：US06603199B1

公开(公告)日：2003-08-05

申请号：US09724739

申请日：2000-11-28

申请人： Anindya Poddar

发明人： Anindya Poddar

IPC分类号： H01L2352

CPC分类号： H01L24/06 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A single tier cavity down integrated circuit package having a die with outer bond pads and staggered inner bond pads is described. The bond pads of the die are assigned to associated supply rings and bond fingers of the package according to a design methodology where in one embodiment at least all bond pads connected to the supply rings are outer bond pads, and staggered inner bond pads are connected to bond fingers. There is further described a method for assigning bond pads of the die to associated supply rings and bond fingers of the package, as well as, a die having staggered bond pads formed in accordance with the method of the present invention.

摘要翻译： 描述了具有具有外接合焊盘和交错内接合焊盘的管芯的单层空腔向下集成电路封装。 模具的接合垫根据设计方法分配给包装的相关联的供应环和粘合指状物，其中在一个实施例中，至少所有连接到供应环的接合垫是外部接合垫，并且交错的内部接合垫连接到 债券手指。 进一步描述了用于将芯片的接合焊盘分配给封装的相关联的供给环和结合指状物的方法，以及具有根据本发明的方法形成的交错键合焊盘的管芯。

公开(公告)号：US20120043660A1

公开(公告)日：2012-02-23

申请号：US12858331

申请日：2010-08-17

申请人： Anindya Poddar ,  Nghia T. Tu ,  Hau Nguyen

发明人： Anindya Poddar ,  Nghia T. Tu ,  Hau Nguyen

IPC分类号： H01L23/488 ,  H01L21/78 ,  H01L23/31 ,  H01L21/50

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L24/97 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method.

摘要翻译： 本发明的一个方面涉及用于封装集成电路的基于箔的方法。 最初，金属箔和光致抗蚀剂层与载体相连。 光致抗蚀剂层被曝光和图案化。 之后，将多个集成电路芯片连接到箔片。 骰子和箔的一部分被包封在模制材料中。 然后基于图案化的光致抗蚀剂层蚀刻箔，以在箔中限定多个器件区域，其中每个器件区域支持集成电路管芯中的至少一个。 本发明的一些方面涉及上述方法中涉及的面板装置。

公开(公告)号：US07923825B2

公开(公告)日：2011-04-12

申请号：US12553919

申请日：2009-09-03

申请人： Jaime A. Bayan ,  Anindya Poddar

发明人： Jaime A. Bayan ,  Anindya Poddar

IPC分类号： H01L23/495

CPC分类号： H01L23/49548 ,  H01L23/3185 ,  H01L23/49537 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/09701 ,  H01L2924/19041

摘要： An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad.

摘要翻译： 描述了一种集成电路封装，其包括集成电路管芯，多个下接触引线和位于管芯和下接触引线上的绝缘基片。 绝缘基板包括形成在基板的底表面上的多个导电上路由迹线。 衬底底面上的迹线将每个下接触引线与相关的I / O焊盘电耦合。