公开(公告)号：US08129272B2

公开(公告)日：2012-03-06

申请号：US12493582

申请日：2009-06-29

Applicant: Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20120025396A1

公开(公告)日：2012-02-02

申请号：US12844959

申请日：2010-07-28

Applicant: Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

Inventor： Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

IPC: H01L23/488

CPC classification number: H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.

Abstract translation: 公开了一种半导体管芯封装。 半导体封装的示例包括散布有第二组半导体管芯的第一组半导体管芯。 来自第一组和第二组的模具沿着第一轴线彼此偏移并且沿着与第一轴线正交的第二轴线相对于彼此交错。 半导体封装的第二示例包括不规则形状的边缘和从封装中的最低半导体管芯上方的半导体管芯到基板的引线接合。

公开(公告)号：US08053880B2

公开(公告)日：2011-11-08

申请号：US12489298

申请日：2009-06-22

Applicant: Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

Inventor： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract translation: 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US09331045B2

公开(公告)日：2016-05-03

申请号：US14399495

申请日：2012-05-07

Applicant: Wei Gu ,  Zhong Lu ,  Cheeman Yu ,  Chin-Tien Chiu ,  En-Yong Tai ,  Min Ni

Inventor： Wei Gu ,  Zhong Lu ,  Cheeman Yu ,  Chin-Tien Chiu ,  En-Yong Tai ,  Min Ni

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L24/75 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/7598 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A laminating device (230) and method are disclosed for laminating semiconductor die (220) on substrates on a panel (200) of substrates. The laminating device (230) includes lamination units (234,236,238,240) that operate independently of each other so that a row or column of semiconductor die (220) may be independently laminated onto a row or column of substrates simultaneously.

Abstract translation: 公开了用于将基板上的半导体管芯（220）层压在基板（200）上的层压装置（230）和方法。 层压装置（230）包括层叠单元（234,236,238,240），其彼此独立地操作，使得半导体管芯（220）的行或列可以独立地层压到基板的行或列上。

公开(公告)号：US20140183727A1

公开(公告)日：2014-07-03

申请号：US14118485

申请日：2011-05-18

Applicant: Zhong Lu ,  Fen Yu ,  Chin Tien Chiu ,  Cheeman Yu ,  Fuqiang Xiao

Inventor： Zhong Lu ,  Fen Yu ,  Chin Tien Chiu ,  Cheeman Yu ,  Fuqiang Xiao

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49866 ,  H01L21/768 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03013 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06145 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48456 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78349 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/85948 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48095

Abstract: A wire bonded structure for a semiconductor device is disclosed. The wire bonded structure comprises a bonding pad; and a continuous length of wire mutually diffused with the bonding pad, the wire electrically coupling the bonding pad with a first electrical contact and a second electrical contact different from the first electrical contact.

Abstract translation: 公开了一种用于半导体器件的引线接合结构。 引线接合结构包括接合焊盘; 以及与所述接合焊盘相互扩散的连续长度的导线，所述线将所述接合焊盘与第一电接触和与所述第一电接触不同的第二电接触电耦合。

公开(公告)号：US08232145B2

公开(公告)日：2012-07-31

申请号：US12614960

申请日：2009-11-09

Applicant: Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

Inventor： Che-Jung Chang ,  Chin-Tien Chiu ,  Cheeman Yu ,  Hem Takiar ,  Jack Chang Chien ,  Ning Liu

IPC: H01L21/00

CPC classification number: G06K19/077 ,  B29C45/14311 ,  B29C45/14647 ,  B29C2045/14327 ,  G06K19/07724 ,  G06K19/07732 ,  H01L23/10 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract translation: 公开了一种闪存卡及其制造方法。 卡包括制造成接收单面或双面盖的半导体封装。 半导体封装的表面可以形成有孔，沟槽和/或戳记。 在形成孔，沟和/或标记之后，可以在注射成型工艺中将盖子附接到包装表面。 在注射成型过程中，熔融的塑料流入与半导体封装的表面互连的孔，沟槽和/或戳痕。 因此，当熔融塑料硬化时，孔，沟槽和/或戳痕确保盖保持牢固地附接到半导体封装。

公开(公告)号：US08053276B2

公开(公告)日：2011-11-08

申请号：US12614981

申请日：2009-11-09

Applicant: Cheeman Yu ,  Chi-Chin Liao ,  Hem Takiar

Inventor： Cheeman Yu ,  Chi-Chin Liao ,  Hem Takiar

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L24/49 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract translation: 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US20150115479A1

公开(公告)日：2015-04-30

申请号：US14399495

申请日：2012-05-07

Applicant: Wei Gu ,  Zhong Lu ,  Cheeman Yu ,  Chin-Tien Chiu ,  En-Yong Tai ,  Min Ni

Inventor： Wei Gu ,  Zhong Lu ,  Cheeman Yu ,  Chin-Tien Chiu ,  En-Yong Tai ,  Min Ni

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/75 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/7598 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A laminating device (230) and method are disclosed for laminating semiconductor die (220) on substrates on a panel (200) of substrates. The laminating device (230) includes lamination units (234,236,238,240) that operate independently of each other so that a row or column of semiconductor die (220) may be independently laminated onto a row or column of substrates simultaneously.

Abstract translation: 公开了用于将基板上的半导体管芯（220）层压在基板（200）上的层压装置（230）和方法。 层压装置（230）包括层叠单元（234,236,238,240），其彼此独立地操作，使得半导体管芯（220）的行或列可以独立地层压到基板的行或列上。

公开(公告)号：US20140346686A1

公开(公告)日：2014-11-27

申请号：US14342157

申请日：2011-09-02

Applicant: Fu Peng ,  Zhong Lu ,  Chin Tien Chiu ,  Cheeman Yu ,  Matthew Chen ,  Weiting Jiang

Inventor： Fu Peng ,  Zhong Lu ,  Chin Tien Chiu ,  Cheeman Yu ,  Matthew Chen ,  Weiting Jiang

IPC: H01L23/544 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L23/28 ,  H01L23/544 ,  H01L23/552 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device.

Abstract translation: 公开了一种包括图形内容的存储设备和使具有图形内容的存储设备的方法。 图形内容形成在释放介质上。 将释放介质和未封装的存储器件放置在模具中并封装。 在模塑料的包封和固化期间，图形内容从释放介质转移到封装的存储器件。

公开(公告)号：US20120081860A1

公开(公告)日：2012-04-05

申请号：US13129510

申请日：2010-10-04

Applicant: Itzhak Pomerantz ,  Shiv Kumar ,  Robert Miller ,  Chin-Tien Chiu ,  Peng Fu ,  Cheeman Yu ,  Hem Takiar ,  Chih Chiang Tung ,  Kaiyou Qian

Inventor： Itzhak Pomerantz ,  Shiv Kumar ,  Robert Miller ,  Chin-Tien Chiu ,  Peng Fu ,  Cheeman Yu ,  Hem Takiar ,  Chih Chiang Tung ,  Kaiyou Qian

IPC: H05K1/14 ,  B32B3/10 ,  B32B3/02 ,  H05K7/00 ,  B32B3/30

CPC classification number: H05K5/0252 ,  G06K19/07 ,  Y10T428/239 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24802

Abstract: A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface.

Abstract translation: 公开了一种记录装置，其包括至少一个预处理表面的表面，以便更好地粘附在表面上的墨。 存储器件的表面可以通过用激光在表面上刻划线或者通过用粒子喷射器形成离散的变形来预处理。 在封装过程中，通过在模板上提供粗糙图案也可以使表面粗糙化。 在另外的实施例中，表面可以被化学预处理以使表面粗糙化和/或增加表面的粘附能。