公开(公告)号：US10573622B2

公开(公告)日：2020-02-25

申请号：US15720480

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Lilia May ,  Edward R. Prack

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/50 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/60

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.

公开(公告)号：US10128225B2

公开(公告)日：2018-11-13

申请号：US15436291

申请日：2017-02-17

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L25/065 ,  H01L23/31

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US10049971B2

公开(公告)日：2018-08-14

申请号：US15478064

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Thomas J. De Bonis ,  Lilia May ,  Rajen S. Sidhu ,  Mukul P. Renavikar ,  Ashay A. Dani ,  Edward R. Prack ,  Carl L. Deppisch ,  Anna M. Prakash ,  James C. Matayabas ,  Jason Jieping Zhang ,  Srinivasa R. Aravamudhan ,  Chang Lin

IPC: H01L21/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.

公开(公告)号：US09824991B2

公开(公告)日：2017-11-21

申请号：US15421340

申请日：2017-01-31

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Tony Dambrauskas ,  Danish Faruqui ,  Mark S. Hlad ,  Edward R. Prack

IPC: H01L21/58 ,  H01L23/00 ,  H01L21/78 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/02118 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76883 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3142 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1162 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81026 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81375 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81913 ,  H01L2224/831 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.

公开(公告)号：US20170229438A1

公开(公告)日：2017-08-10

申请号：US15436291

申请日：2017-02-17

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L25/065 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L25/50 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US20170033068A1

公开(公告)日：2017-02-02

申请号：US15293103

申请日：2016-10-13

Applicant: Intel Corporation

Inventor： Edward R. Prack

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/288 ,  H01L21/4867 ,  H01L21/768 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/53228 ,  H01L23/5328 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11505 ,  H01L2224/11849 ,  H01L2224/13147 ,  H01L2924/14 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及焊接和铜互连结构的形成以及相关联的技术和配置。 在一个实施例中，一种方法包括提供集成电路（IC）基板，并使用油墨沉积工艺，粘合剂印刷系统或粉末激光烧结系统将可焊接材料沉积在IC基板上。 在另一实施例中，一种方法包括提供集成电路（IC）基板，并使用添加工艺在铜基板上沉积铜粉以形成铜互连结构。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160307869A1

公开(公告)日：2016-10-20

申请号：US15196866

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Danish Faruqui ,  Edward R. Prack ,  Sergei L. Voronov ,  David K. Wilkinson, JR. ,  Tony Dambrauskas ,  Lars D. Skoglund ,  Yoshihiro Tomita ,  Mihir A. Oka ,  Rajen C. Dias

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L24/83 ,  H01L21/56 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29323 ,  H01L2224/29324 ,  H01L2224/29347 ,  H01L2224/29366 ,  H01L2224/29387 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81132 ,  H01L2224/83132 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83224 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10332 ,  H01L2924/10335 ,  H01L2924/10525 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2224/27 ,  H01L2924/0535 ,  H01L2924/01023 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die adhesive films and package assemblies and systems incorporating such die adhesive films. A die adhesive film may be transparent to a first wavelength of light and photoreactive to a second wavelength of light. In some embodiments, the die adhesive film may be applied to a back or “inactive” side of a die, and the die surface may be detectable through the die adhesive film. The die adhesive film may be cured and/or marked with laser energy having the second wavelength of light. The die adhesive film may include a thermochromic dye and/or nanoparticles configured to provide laser mark contrast. UV laser energy may be used to remove the die adhesive film in order to expose underlying features such as TSV pads.

Abstract translation: 本公开的实施例涉及用于集成电路（IC）封装的芯片粘合膜，以及用于形成和去除模具粘合剂膜和封装组件的方法以及结合这种模具粘合剂膜的系统。 模具粘合剂膜可以对第一波长的光是透明的，并且对第二波长的光进行光反应。 在一些实施例中，模具粘合剂膜可以施加到模具的背面或“非活性”侧，并且模具表面可以通过模具粘合剂膜检测。 模具粘合剂膜可以用具有第二波长的光的激光能量固化和/或标记。 模具粘合剂膜可以包括被配置为提供激光标记对比度的热变色染料和/或纳米颗粒。 可以使用UV激光能量去除模具粘合剂膜以暴露诸如TSV焊盘之类的底层特征。

公开(公告)号：US09165914B2

公开(公告)日：2015-10-20

申请号：US13895546

申请日：2013-05-16

Applicant: Intel Corporation

Inventor： Rahul N. Manepalli ,  Mohit Mamodia ,  David Xu ,  Javier Soto Gonzalez ,  Edward R. Prack

IPC: H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/24 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2924/10253 ,  H01L2924/10523 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将图案化的模具背面薄膜（DBF）附接到模具的背面，其中图案化的DBF包括围绕设置在模具背面的至少一个穿过硅通孔（TSV）垫的开口。