Patent search ap:("INTEL CORPORATION") AND inv:"Islam A. Salama" Page 2

11.

发明授权
Architecture for seamless integrated display system 有权
Title translation: 无缝集成显示系统架构

公开(公告)号：US09361059B2

公开(公告)日：2016-06-07

申请号：US13715193

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Johanna Swan , Uygar Avci , Islam A. Salama , Ravi Pallarisetty

IPC: G09G5/00 , G06F3/14 , G09F9/302 , G09F9/35 , H01L27/32 , G09G3/20 , G02F1/1333 , G02F1/1345

CPC classification number: G06F3/1446 , G02F1/13336 , G02F1/1345 , G09F9/3026 , G09F9/35 , G09G3/20 , G09G5/003 , G09G5/14 , G09G2300/026 , G09G2320/02 , G09G2340/14 , G09G2360/04 , H01L27/3293

Abstract: Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive circuitry can be removably coupled with a display device via an array of contact members. The display device can include image-producing elements or pixels that can be selectively driven by the backpanel device via corresponding portions of the array of contact members. Multiple display devices can be disposed adjacently on one or more backpanel devices such that an image displayed across the multiple display devices appears seamless.

Abstract translation: 这里通常描述无缝显示器的系统和方法的实施例。在一些实施例中，包括显示器驱动电路的背板装置可以通过接触构件阵列可移除地与显示装置耦合。显示装置可以包括图像产生元件或可以由背板装置通过接触构件阵列的相应部分选择性地驱动的图像。多个显示设备可以相邻地布置在一个或多个背板设备上，使得跨越多个显示设备显示的图像看起来是无缝的。

12.

发明授权
Device and method of very high density routing used with embedded multi-die interconnect bridge 有权

公开(公告)号：US12014989B2

公开(公告)日：2024-06-18

申请号：US18091048

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Robert Alan May , Wei-Lun Kane Jen , Jonathan L. Rosch , Islam A. Salama , Kristof Darmawikarta

IPC: H01L23/538 , H01L21/48 , H01L21/683 , H01L23/00 , H01L25/00 , H01L25/065

CPC classification number: H01L23/5381 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/16 , H01L25/0655 , H01L25/50 , H01L2221/68372 , H01L2224/16227

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

13.

发明授权
Microelectronic device with embedded die substrate on interposer 有权

公开(公告)号：US11430740B2

公开(公告)日：2022-08-30

申请号：US16474026

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Robert Alan May , Islam A. Salama , Sri Ranga Sai Boyapati , Sheng Li , Kristof Darmawikarta , Robert L. Sankman , Amruthavalli Pallavi Alur

IPC: H01L23/52 , H01L23/31 , H01L25/07 , H01L25/11 , H01L23/538 , H01L21/56 , H01L21/683 , H01L23/00 , H01L25/065

Abstract: Microelectronic devices with an embedded die substrate on an interposer are described. For example, a microelectronic device includes a substrate housing an embedded die. At least one surface die is retained above a first outermost surface of the substrate. An interposer is retained proximate a second outermost surface of the substrate.

14.

发明申请
DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGE 有权

公开(公告)号：US20210280517A1

公开(公告)日：2021-09-09

申请号：US16322423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Robert Alan May , Wei-Lun Kane Jen , Jonathan L. Rosch , Islam A. Salama , Kristof Darmawikarta

IPC: H01L23/538 , H01L25/065 , H01L23/00 , H01L21/683 , H01L21/48 , H01L25/00

Abstract: A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

15.

发明授权
Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same 有权

公开(公告)号：US11043457B2

公开(公告)日：2021-06-22

申请号：US16889735

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Amruthavalli Pallavi Alur , Sri Ranga Sai Boyapati , Robert Alan May , Islam A. Salama , Robert L. Sankman

IPC: H01L23/492 , H01L23/538 , H01L23/498 , H01L23/00 , H01L25/065 , H01L21/48 , H01L25/00 , H01L25/18 , H01L23/31 , H01L21/66 , H01L21/683 , H01L25/11

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

16.

发明授权
Integrated circuit structures with recessed conductive contacts for package on package 有权

公开(公告)号：US10424561B2

公开(公告)日：2019-09-24

申请号：US15863821

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee , Islam A. Salama , Ram S. Viswanath , Robert L. Sankman , Babak Sabi , Sri Chaitra Jyotsna Chavali

IPC: H01L23/00 , H01L23/13 , H01L23/48 , H01L25/10 , H01L23/498 , H01L25/065

Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.

17.

发明授权
Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same 有权

公开(公告)号：US10163798B1

公开(公告)日：2018-12-25

申请号：US15853330

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Amruthavalli Pallavi Alur , Sri Ranga Sai Boyapati , Robert Alan May , Islam A. Salama , Robert L. Sankman

IPC: H01L25/10 , H01L23/538 , H01L23/498 , H01L23/00 , H01L25/065 , H01L21/48 , H01L25/00 , H01L25/18 , H01L21/66 , H01L21/683 , H01L25/11 , H01L23/492

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.