公开(公告)号：US20130207306A1

公开(公告)日：2013-08-15

申请号：US13485307

申请日：2012-05-31

Applicant: Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Hsien-Wen Liu ,  Yi-Lin Tsai ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: B29C43/18 ,  H01L21/56

CPC classification number: B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

Abstract translation: 一种方法包括将聚合物模塑到包装部件上。 模制步骤包括在第一温度下进行的第一模塑阶段和在与第一温度不同的第二温度下进行的第二模塑阶段。

公开(公告)号：US20130187270A1

公开(公告)日：2013-07-25

申请号：US13452140

申请日：2012-04-20

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.

Abstract translation: 封装包括在管芯的顶表面处具有导电焊盘的芯片，在导电焊盘上方并连接到导电焊盘的柱形凸块，以及重新分配线，并且连接到螺柱凸块。 电连接器在再分配线上电连接。

公开(公告)号：US20130119533A1

公开(公告)日：2013-05-16

申请号：US13297992

申请日：2011-11-16

Applicant: Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Chih-Hao Chen ,  Long Hua Lee ,  Chun-Hsing Su ,  Yi-Lin Tsai ,  Kung-Chen Yeh ,  Chung Yu Wang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/78 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Abstract translation: 晶片级封装包括结合在支撑晶片上的半导体管芯。 半导体管芯在其衬底上至少有一个台阶凹槽。 在半导体管芯和支撑晶片之间形成底部填充层。 此外，底部填充层的高度受到台阶凹槽的限制。 在晶片级封装的制造过程中，台阶凹槽有助于减小晶片级封装上的应力。

公开(公告)号：US20130037990A1

公开(公告)日：2013-02-14

申请号：US13208197

申请日：2011-08-11

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56

CPC classification number: H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

Abstract translation: 模制系统的底部追逐和顶部追逐形成容纳模制载体和一个或多个装置的空腔。 模制载体被放置在由引导部件限定的期望位置。 引导部件可以完全在腔内，或者延伸到底部追逐的表面之上，并延伸到顶部追逐和底部追逐的接触边缘上，使得在顶部追逐的边缘和边缘之间存在间隙 由模制材料填充以覆盖模制载体的边缘的模制载体。 释放部件可以与顶部追逐和/或底部追逐相关联，其可以是具有释放膜的多个带辊或底部追逐内的多个真空孔，或者具有底部追逐的多个底部销 。

公开(公告)号：US09679783B2

公开(公告)日：2017-06-13

申请号：US13208197

申请日：2011-08-11

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US08962392B2

公开(公告)日：2015-02-24

申请号：US13418868

申请日：2012-03-13

Applicant: Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

Inventor： Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

IPC: H01L21/50 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/568 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

Abstract translation: 一种方法包括将载体粘合在顶模上。 该方法还包括固化设置在基底和顶模之间的底部填充物。 该方法还包括在固化期间在载体上施加力。 该方法还包括从顶模移除载体。

公开(公告)号：US08872326B2

公开(公告)日：2014-10-28

申请号：US13597868

申请日：2012-08-29

Applicant: Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung

IPC: H01L23/48

CPC classification number: H01L23/562 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/24 ,  H01L24/27 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00011

Abstract: The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.

Abstract translation: 上述形成半导体器件封装的机构由于相对简单的工艺流程而提供了低成本的制造工艺。 通过形成具有再分布层的互连结构以使得能够在封装结构下方的一个或多个管芯接合，整体封装的翘曲大大降低。 此外，形成互连结构，而不使用模塑料，这减少了颗粒污染。 翘曲和颗粒污染的减少会提高产量。 此外，形成的半导体器件封装具有低的形状因数，其中一个或多个管芯装配在封装结构和互连结构之间的空间的下方。

公开(公告)号：US20130087916A1

公开(公告)日：2013-04-11

申请号：US13270850

申请日：2011-10-11

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Yi-Hang Lin ,  Tsan-Hua Tung

IPC: H01L23/498 ,  H01L21/60 ,  H01L21/50

CPC classification number: H01L21/78 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

公开(公告)号：US09064879B2

公开(公告)日：2015-06-23

申请号：US13228244

申请日：2011-09-08

Applicant: Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.

Abstract translation: 公开了利用新颖的芯片附着膜的半导体器件的封装方法和结构。 在一个实施例中，封装半导体器件的方法包括提供载体晶片并且在载体晶片上形成包括聚合物的管芯附着膜（DAF）。 多个模具附接到DAF，并且多个管芯被封装。 至少载体晶片从封装的管芯移除，并且封装的管芯被切割。

公开(公告)号：US09000584B2

公开(公告)日：2015-04-07

申请号：US13338820

申请日：2011-12-28

Applicant: Jing-Cheng Lin ,  Jui-Pin Hung ,  Nai-Wei Liu ,  Yi-Chao Mao ,  Wan-Ting Shih ,  Tsan-Hua Tung

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Nai-Wei Liu ,  Yi-Chao Mao ,  Wan-Ting Shih ,  Tsan-Hua Tung

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

Abstract translation: 提供了在半导体器件基板上形成模制化合物以使得晶片级封装（WLP）中的扇出结构能够实现的机制。 这些机构涉及覆盖围绕接触垫的绝缘层的表面的部分。 这些机制提高了包装的可靠性和包装过程的过程控制。 这些机理还降低了界面分层的风险，并且在后续处理过程中绝缘层过度消除气泡。 这些机制进一步改善了平面化终点。 通过利用接触焊盘和绝缘层之间的保护层，可以减少铜外扩散，并且还可以提高接触焊盘和绝缘层之间的粘附。