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    Shielded liquid encapsulated semiconductor device and method for making the same
    11.
    发明授权
    Shielded liquid encapsulated semiconductor device and method for making the same 失效
    屏蔽液体封装半导体器件及其制造方法

    公开(公告)号：US5436203A

    公开(公告)日：1995-07-25

    申请号：US270602

    申请日：1994-07-05

    Applicant: Paul T. Lin

    Inventor： Paul T. Lin

    IPC: H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L21/60

    CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/552 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49146

    Abstract: A semiconductor (30) is shielded from electromagnetic interference by a combination of a reference plane (22) of a circuitized substrate (12) and two different encapsulants. The first encapsulant (38) is an electrically insulative encapsulant which mechanically protects a semiconductor die (32). The first encapsulant is constrained by a dam structure (40) so as not to encapsulate conductive reference pads (18) which are electrically connected to the reference plane by conductive vias (20). A second encapsulant (42) is dispensed over the first encapsulant and is in contact with the reference pads. The second encapsulant is an electrically conductive encapsulant, and is preferably made of a precursor material having the same or similar properties as that of the first encapsulant, but is filled with conductive filler particles to establish electrical conductivity of the encapsulant. Accordingly, the semiconductor die is effectively shielded from both the top and bottom by the electrically conductive encapsulant and the reference plane.

    Abstract translation: 半导体（30）通过电路化基板（12）的参考平面（22）和两个不同的密封剂的组合来屏蔽电磁干扰。 第一密封剂（38）是机械保护半导体管芯（32）的电绝缘密封剂。 第一密封剂由坝结构（40）约束，以便不封装通过导电通孔（20）电连接到参考平面的导电参考焊盘（18）。 第二密封剂（42）被分配在第一密封剂上并与参考焊盘接触。 第二密封剂是导电密封剂，并且优选由具有与第一密封剂相同或相似性质的前体材料制成，但填充有导电填料颗粒以建立密封剂的导电性。 因此，半导体管芯通过导电密封剂和参考平面被有效地屏蔽顶部和底部两者。

    Semiconductor device having an insertable heat sink and method for mounting the same
    12.
    发明授权
    Semiconductor device having an insertable heat sink and method for mounting the same 失效
    具有可插入散热器的半导体器件及其安装方法

    公开(公告)号：US5216283A

    公开(公告)日：1993-06-01

    申请号：US519375

    申请日：1990-05-03

    Applicant: Paul T. Lin

    Inventor： Paul T. Lin

    IPC: H01L23/10 ,  H01L23/433

    CPC classification number: H01L23/10 ,  H01L23/4334 ,  H01L2224/32188 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/181

    Abstract: A semiconductor device is disclosed having an electronic component mounted to a mounting surface opposite a heat transfer surface of a die support member. The electronic component includes a plurality of bonding pads each electrically coupled to a plurality of package leads by a number of inner leads. A package body encloses the electronic component, the inner leads, the proximal ends of the package leads and the mounting surface of the die support member. The package body includes an opening exposing a portion of the heat transfer surface of the die support member. An insertable thermally conductive heat sink extends into the opening in the package body making thermal contact with the heat transfer surface of the die support member. A thermally conductive electrically insulating adhesive joins the heat sink to the package body securing the heat sink to the package body. In the assembly process, the package body is formed prior to attachment of the heat sink. During the process of soldering the package leads of the semiconductor device to a mounting substrate, gasses within the package body can escape through the opening before excessive pressure buildup occurs within the package body.

    Abstract translation: 公开了一种半导体器件，其具有安装到与模具支撑构件的传热表面相对的安装表面的电子部件。 电子部件包括多个接合焊盘，每个焊盘通过多个内部引线电耦合到多个封装引线。 封装体包围电子部件，内部引线，封装引线的近端和管芯支撑构件的安装表面。 包装体包括暴露模具支撑构件的传热表面的一部分的开口。 可插入的导热散热器延伸到封装主体中的开口中，与模具支撑构件的传热表面热接触。 导热电绝缘粘合剂将散热器连接到将散热器固定到封装主体的封装体。 在组装过程中，在安装散热器之前形成包装体。 在将半导体器件的封装引线焊接到安装基板的过程中，封装体内的气体可以在封装主体内发生过大的压力累积之前通过开口逸出。

    Method for fabricating multiple electronic devices within a single carrier structure
    13.
    发明授权
    Method for fabricating multiple electronic devices within a single carrier structure 失效
    在单载波结构内制造多个电子装置的方法

    公开(公告)号：US5114880A

    公开(公告)日：1992-05-19

    申请号：US680890

    申请日：1991-05-28

    Applicant: Paul T. Lin

    Inventor： Paul T. Lin

    IPC: H01L21/48 ,  H01L21/56

    CPC classification number: H01L21/4842 ,  H01L21/565 ,  H01L2224/48091 ,  H01L2224/48247 ,  Y10T29/49121

    Abstract: The disclosed invention comprises multiple semiconductor devices within a single carrier structure. In accordance with one embodiment of the invention, a plurality of semiconductor die are coupled to the leads of a leadframe and are encapsulated by individual package bodies. A carrier structure is formed which encircles all of the die and encapsulates portions of the distal ends of the leads. The extreme distal portions of the leads extend through the carrier to form contact points which are used to access the semiconductor die. By having multiple devices within a single carrier, productivity is improved and costs associated with leadframe and carrier structure materials are reduced.

    Abstract translation: 所公开的发明包括在单载波结构内的多个半导体器件。 根据本发明的一个实施例，多个半导体管芯耦合到引线框架的引线并被单个封装体封装。 形成一个载体结构，其包围所有的管芯并且封装引线的远端部分。 引线的极端部分延伸穿过载体以形成用于接近半导体管芯的接触点。 通过在单个载体内具有多个装置，提高了生产效率并降低了与引线框和载体结构材料相关的成本。

    Pad array carrier IC device using flexible tape
    14.
    发明授权
    Pad array carrier IC device using flexible tape 失效
    垫阵列载体IC器件采用软磁带

    公开(公告)号：US5045921A

    公开(公告)日：1991-09-03

    申请号：US457002

    申请日：1989-12-26

    Applicant: Paul T. Lin ,  Howard P. Wilson

    Inventor： Paul T. Lin ,  Howard P. Wilson

    IPC: H01L23/057 ,  H01L23/495 ,  H01L23/498 ,  H05K3/30 ,  H05K3/36

    CPC classification number: H05K3/303 ,  H01L23/057 ,  H01L23/49572 ,  H01L23/49827 ,  H01L23/4985 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H05K2201/10568 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K3/363 ,  Y02P70/613

    Abstract: An electronic pad array carrier IC device for mounting on a printed circuit board (PCB) or flex circuit substrate has a thin, flexible "tape" substrate having a plurality of traces. The substrate may be a polyimide or other material that can withstand relatively large lateral mechanical displacement. An integrated circuit die is mounted in proximity with or on the substrate and electrical connections between the integrated circuit chip and the traces are made by any conventional means. The substrate traces are provided at their outer ends with solder balls or pads for making connections to the PCB. A package body covers the die, which body may be optionally used to stand off the package a set distance from the PCB so that the solder balls will form the proper concave structure. Alternatively, a carrier structure may be provided around the periphery of the substrate to add rigidity during handling, testing and mounting, but which may also provide the stand-off function. The thin, flexible substrate can absorb a relatively large lateral or even vertical mechanical displacement over a rather large package area that may accommodate as few as 20 or as many 500 or more connections. The substrate may be optionally transparent or translucent to permit inspection of the bonds after mounting to the PCB. The PCB or flex circuit may also be transparent or translucent for bond inspection purposes. The solder pads or balls may be joined to a via through the substrate at least partially filled with electrically conductive material to permit back side testing of the carrier before or after mounting of the package to the PCB. Additionally, a heat sink structure may be directly bonded to the die in the pad array carrier IC device.

    Abstract translation: 用于安装在印刷电路板（PCB）或柔性电路基板上的电子焊盘阵列载体IC器件具有具有多个迹线的薄的，柔性的“带”衬底。 衬底可以是聚酰亚胺或能承受相对大的横向机械位移的其他材料。 集成电路管芯安装在衬底附近或衬底上，并且集成电路芯片和迹线之间的电连接通过任何常规方式制成。 衬底迹线在其外端设置有用于连接到PCB的焊球或焊盘。 封装体覆盖模具，该主体可以可选地用于将封装与PCB隔开一定距离，使得焊球将形成适当的凹形结构。 或者，可以在基板的周边周围设置载体结构，以在处理，测试和安装期间增加刚性，但是也可以提供隔离功能。 薄的柔性基底可以在相当大的封装区域上吸收相对较大的侧向或甚至垂直的机械位移，其可以容纳少至20个或多于500个或更多个连接。 衬底可以是任选的透明或半透明的，以允许在安装到PCB之后检查焊接。 PCB或柔性电路也可以是透明或半透明的，用于粘合检查目的。 焊盘或球可以通过至少部分地填充有导电材料的基板连接到通孔，以允许在将封装安装到PCB之前或之后的载体的背侧测试。 此外，散热器结构可以直接接合到焊盘阵列载体IC器件中的管芯。

    Method of removing contaminants
    19.
    发明授权
    Method of removing contaminants 失效
    去除污染物的方法

    公开(公告)号：US5300187A

    公开(公告)日：1994-04-05

    申请号：US940108

    申请日：1992-09-03

    Applicant: Israel A. Lesk ,  Young Limb ,  Philip J. Tobin ,  John Franka ,  Paul T. Lin ,  Jonathan C. Dahm ,  Gary L. Huffman ,  Bich-Yen Nguyen

    Inventor： Israel A. Lesk ,  Young Limb ,  Philip J. Tobin ,  John Franka ,  Paul T. Lin ,  Jonathan C. Dahm ,  Gary L. Huffman ,  Bich-Yen Nguyen

    IPC: H01L21/306 ,  B44C1/22

    CPC classification number: H01L21/02046 ,  Y10S438/906

    Abstract: Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.

    Abstract translation: 通过将半导体材料加热到卤素化合物将分解成卤素原子的最低温度的范围内的温度而不使用紫外线照射并与存在于半导体材料上的污染物反应并且与半导体材料的最高温度 800℃，其中在半导体材料上形成小于或等于约50埃的氧化物。 其中半导体材料被加热的环境是由非反应性气体和卤素化合物组成的环境，其至少足以从半导体材料中除去大量污染物的时间。

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