公开(公告)号：US20170033059A1

公开(公告)日：2017-02-02

申请号：US14809983

申请日：2015-07-27

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Uei-Ming JOW ,  Jong-Hoon LEE

IPC: H01L23/58 ,  H01L21/765 ,  H01L49/02

CPC classification number: H01L23/585 ,  H01L21/765 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

Abstract translation: 公开了一种互连元件的多层接地屏蔽结构。 接地屏蔽结构可以包括接地屏蔽结构的第一图案化层，接地屏蔽结构的第二图案化层，以及在第一图案化层和第二图案化层之间的间隔物。 第一图案化层包括根据第一图案在第一图案化层内互连的第一导电元件。 第二图案化层包括根据第二图案在第二图案化层内互连的第二导电元件。

公开(公告)号：US20160365196A1

公开(公告)日：2016-12-15

申请号：US14736219

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Hong Bok WE ,  Kyu-Pyung HWANG

IPC: H01G4/228 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/228 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

Abstract translation: 无源分立器件可以包括第一不对称端子和第二非对称端子。 无源分立器件还可以包括扩展以电耦合到第一不对称端子的第一侧和第二侧的第一内部电极。 无源分立器件还可以包括扩展以电耦合到第二不对称端子的第一侧和第二侧的第二内部电极。

公开(公告)号：US20160172274A1

公开(公告)日：2016-06-16

申请号：US14572760

申请日：2014-12-16

Applicant: Qualcomm Incorporated

Inventor： Jung Ho YOON ,  Young Kyu SONG ,  Uei-Ming JOW ,  Jong-Hoon LEE ,  Xiaonan ZHANG

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/66 ,  H01L23/522

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L23/492 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49568 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A semiconductor package according to some examples may include a first portion of a support plate configured as an RF signal connection, a semiconductor die thermally coupled to a second portion of the support plate to dissipate heat, a first redistribution layer positioned in close proximity to a second redistribution layer to capacitively couple the first redistribution layer to the second redistribution layer, a first via extending between the first portion and the first redistribution layer, and a second via in close proximity to the first via to capacitively couple the second via to the first via.

Abstract translation: 根据一些示例的半导体封装可以包括被配置为RF信号连接的支撑板的第一部分，热耦合到支撑板的第二部分以散热的半导体管芯，第一再分配层位于 第二再分布层，以将第一再分布层电容耦合到第二再分配层，在第一部分和第一再分布层之间延伸的第一通孔，以及紧邻第一通孔的第二通孔，以将第二通孔电容耦合到第一通路 通过。

公开(公告)号：US20150228707A1

公开(公告)日：2015-08-13

申请号：US14179202

申请日：2014-02-12

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Yunseo PARK ,  Xiaonan ZHANG ,  Ryan David LANE ,  Aristotele HADJICHRISTOS

IPC: H01L49/02 ,  H01L23/00

CPC classification number: H01L28/10 ,  H01L23/3192 ,  H01L23/5227 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/16225 ,  H01L2924/01029 ,  H01L2924/30107

Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

Abstract translation: 晶圆级封装（WLP）上的电感器设计不需要将焊球沉淀在芯片上，因为焊球形成电感器的一部分。 电感器上的一个端子耦合到管芯，另一个端子耦合到管芯上的单个焊球，并且与电感器机械接触的剩余焊球保持电浮动。 所产生的器件具有更好的电感，直流（DC）电阻，电路板级可靠性（BLR）和品质因数（Q）。

公开(公告)号：US20170201291A1

公开(公告)日：2017-07-13

申请号：US15151285

申请日：2016-05-10

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun GU ,  Chengjie ZUO ,  Steve FANELLI ,  Thomas GEE ,  Young Kyu SONG

IPC: H04B1/48 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L21/762 ,  H01L23/60 ,  H01L49/02 ,  H01L21/84 ,  H01L21/768 ,  H01L27/12 ,  H01L23/66

CPC classification number: H04B1/48 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/66 ,  H01L27/1203 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01L29/0649 ,  H01L2223/6672 ,  H01L2223/6677

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

公开(公告)号：US20160276173A1

公开(公告)日：2016-09-22

申请号：US14663342

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Kyu-Pyung HWANG ,  Jae Sik LEE

IPC: H01L21/48 ,  H01L49/02 ,  H01L23/498

CPC classification number: H01L21/4846 ,  H01G4/33 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3192 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/642 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L28/60 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/16238 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4661

Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.

Abstract translation: 扇出晶片级封装结构可以包括多层再分配层（RDL）。 多层RDL可以被配置为与嵌入式电容器的端子耦合。 根据所选择的等效串联电阻（ESR）控制模式，多层RDL可以包括具有比多层RDL的其它部分更少的层的部分。

公开(公告)号：US20160183386A1

公开(公告)日：2016-06-23

申请号：US14617864

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Layal ROUHANA ,  Kyu-Pyung HWANG ,  Omar James BCHIR

IPC: H05K3/46 ,  H05K3/32 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/167 ,  H05K1/181 ,  H05K3/1258 ,  H05K3/321 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/0545 ,  Y02P70/611

Abstract: Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

Abstract translation: 提供了用于控制电容器的等效串联电阻（ESR）的方法和装置。 示例性装置包括具有接地侧的基板，安装在基板的接地侧上并具有ESR和端子的电容器，耦合到端子的电阻图案以及耦合到电阻图案的多个通孔。 电阻模式被配置为控制ESR。 电阻图案可以由电阻浆料形成。 电阻图案可以形成为具有大致45度至基本上135度的弧度的大致半圆形状。 电容器可以是表面贴装器件。 电阻图案可以形成为陆侧电容器安装垫，通孔或两者的形状。

公开(公告)号：US20160049458A1

公开(公告)日：2016-02-18

申请号：US14459316

申请日：2014-08-14

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Kyu-Pyung HWANG

IPC: H01L49/02

CPC classification number: H01L28/10

Abstract: A semiconductor structure according to some examples may include an LC component for use in PMIC applications. The semiconductor structure may have a first conductive coil mounted on an upper surface of a substrate, the first conductive coil surrounding a magnetic core; an output located on a surface of the first conductive coil and coupled to the coil; a dielectric layer located on a surface of the output; and an upper conductive element located on a surface of the dielectric layer, wherein the upper conductive element, the dielectric layer, and the output form a capacitor; and the first conductive coil and the magnetic core form an inductor. The semiconductor structure may also include a second conductive coil located in a same horizontal plane as the first conductive coil, the second conductive coil surrounding a magnetic core where the first conductive coil and the second conductive coil form a fishbone pattern.

Abstract translation: 根据一些示例的半导体结构可以包括用于PMIC应用中的LC组件。 半导体结构可以具有安装在基板的上表面上的第一导电线圈，第一导电线圈围绕磁芯; 输出，位于所述第一导电线圈的表面上并且耦合到所述线圈; 位于输出表面上的电介质层; 以及位于所述电介质层的表面上的上导电元件，其中所述上导电元件，所述电介质层和所述输出形成电容器; 并且第一导电线圈和磁芯形成电感器。 半导体结构还可以包括位于与第一导电线圈相同的水平平面中的第二导电线圈，第二导电线圈围绕磁芯，其中第一导电线圈和第二导电线圈形成鱼骨图案。

公开(公告)号：US20150091132A1

公开(公告)日：2015-04-02

申请号：US14042140

申请日：2013-09-30

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook KIM ,  Kyu-Pyung HWANG ,  Young Kyu SONG ,  Changhan Hobie YUN

IPC: H01L21/52 ,  H01L23/04 ,  H01L21/48 ,  H01L49/02 ,  H01L23/13

CPC classification number: H01L21/52 ,  H01L21/4817 ,  H01L23/04 ,  H01L23/13 ,  H01L23/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package. A continuous or uninterrupted stiffener structure is designed with a recessed groove, such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Abstract translation: 用于防止半导体封装中的半导体衬底翘曲的系统和方法。 连续或不间断的加强结构设计有凹槽，使得诸如高密度电容器的无源部件容纳在凹槽内。 具有凹槽的加强结构使用各向异性导电膜（ACF）或各向异性导电膏（ACP）附着到半导体衬底上。 具有凹槽的加强结构围绕可形成在半导体衬底上的一个或多个半导体器件。 具有凹槽的加强结构不延伸超过半导体衬底的水平边界。