公开(公告)号：US11516332B2

公开(公告)日：2022-11-29

申请号：US15811570

申请日：2017-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shi-Yun Cho ,  Ji-Hyun Jung ,  Ho-Jin Lee ,  Young-Min Lee ,  Ho-Seong Seo ,  Youn-Ho Choi

IPC: G06F1/16 ,  G06F3/0488 ,  H04M1/724 ,  H04B1/3827

Abstract: A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.

公开(公告)号：US10109665B2

公开(公告)日：2018-10-23

申请号：US15630063

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Kwangjin Moon ,  Seokho Kim ,  Sukchul Bang ,  Jin Ho An ,  Naein Lee

IPC: H01L27/146

Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

公开(公告)号：US09343361B2

公开(公告)日：2016-05-17

申请号：US14072777

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L21/76 ,  H01L21/326 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US08927426B2

公开(公告)日：2015-01-06

申请号：US13766326

申请日：2013-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Gilheyun Choi ,  YongSoon Choi ,  Byung Lyul Park ,  Hyunsoo Chung

IPC: H01L21/302 ,  H01L29/40 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer.

Abstract translation: 描述了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面打开并部分地穿透衬底的孔，形成部分填充孔的牺牲层，在部分填充有牺牲层的孔中形成通孔，形成通孔绝缘 通孔和衬底之间的层，并且使通孔穿过衬底的底表面。 形成牺牲层可以包括在衬底上形成绝缘的可流动层，并且收缩绝缘流动层以形成固化的可流动层。

公开(公告)号：US20130207242A1

公开(公告)日：2013-08-15

申请号：US13766326

申请日：2013-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-Kyu Kang ,  Kyu-Ha Lee ,  Gilheyun Choi ,  YongSoon Choi ,  Byung Lyul Park ,  Hyunsoo Chung

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer.

Abstract translation: 描述了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面打开并部分地穿透衬底的孔，形成部分填充孔的牺牲层，在部分填充有牺牲层的孔中形成通孔，形成通孔绝缘 通孔和衬底之间的层，并且使通孔穿过衬底的底表面。 形成牺牲层可以包括在衬底上形成绝缘的可流动层，并且收缩绝缘流动层以形成固化的可流动层。

公开(公告)号：US20240186247A1

公开(公告)日：2024-06-06

申请号：US18211316

申请日：2023-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Jun JEON ,  Ho-Jin Lee

IPC: H01L23/528 ,  H01L23/48 ,  H01L27/06 ,  H01L29/417

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L27/0629 ,  H01L28/40 ,  H01L29/41766

Abstract: A semiconductor device includes: a substrate including a first face, on which an active area is formed, and a second face opposite to the first face; an electronic element formed on the active area; a front wiring structure disposed on the first face of the substrate and connected to the electronic element; a trench capacitor filling at least a portion of a back trench extending into the substrate from the second face of the substrate; a back wiring structure disposed on the second face of the substrate and connected to the trench capacitor; and a through-via extending through the substrate to electrically connect the electronic element and the back wiring structure to each other.

公开(公告)号：US11798906B2

公开(公告)日：2023-10-24

申请号：US17551548

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0221 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US11469202B2

公开(公告)日：2022-10-11

申请号：US17029639

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min Son ,  Jeong-Gi Jin ,  Jin-Ho An ,  Jin-Ho Chun ,  Kwang-Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.

公开(公告)号：US09806004B2

公开(公告)日：2017-10-31

申请号：US14953857

申请日：2015-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Byunglyul Park ,  Jisoon Park ,  Jinho An

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03845 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/0601 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/16146 ,  H01L2224/92 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00012 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/03 ,  H01L21/304

Abstract: Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

公开(公告)号：US20150093896A1

公开(公告)日：2015-04-02

申请号：US14566828

申请日：2014-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Ho-Jin Lee ,  Pil-Kyu Kang ,  Byung Lyul Park ,  Hyunsoo Chung ,  Gilheyun Choi

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The inventive concept provides semiconductor devices having through-vias and methods for fabricating the same. The method may include forming a via-hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a via-insulating layer having a first thickness on a bottom surface of the via-hole and a second thickness smaller than the first thickness on an inner sidewall of the via-hole, forming a through-via in the via-hole which the via-insulating layer is formed in, and recessing a bottom surface of the substrate to expose the through-via. Forming the via-insulating layer may include forming a flowable layer on the substrate, and converting the flowable layer into a first flowable chemical vapor deposition layer having the first thickness on the bottom surface of the via-hole.

Abstract translation: 本发明构思提供了具有通孔的半导体器件及其制造方法。 该方法可以包括形成朝向衬底的顶表面开口并部分地穿透衬底的通孔，在通孔的底表面上形成具有第一厚度的通孔绝缘层，并且小于第一厚度的第二厚度 在通孔的内侧壁上的厚度，在形成通孔绝缘层的通孔中形成通孔，并使基板的底表面凹陷以露出通孔。 形成通孔绝缘层可以包括在基板上形成可流动层，并且将可流动层转化为具有第一厚度的第一可流动化学气相沉积层，其在通孔的底表面上。