公开(公告)号：US20140154842A1

公开(公告)日：2014-06-05

申请号：US14174988

申请日：2014-02-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/56 ,  H01L21/78 ,  H01L21/673 ,  H01L21/768

CPC classification number: H01L21/56 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/673 ,  H01L21/67333 ,  H01L21/67763 ,  H01L21/68 ,  H01L21/683 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract translation: 半导体封装的制造方法包括以下步骤：提供在其表面上形成有凹部和释放层的载体; 在凹部中的脱模层上设置芯片; 在芯片和释放层上形成密封剂; 去除释放层和载体; 并在密封剂和芯片上形成电路结构。 凹部的设计有助于芯片对准以防止其移位，从而提高产品的可靠性。 还提供了通过制造方法制造的半导体封装。

公开(公告)号：US10049955B2

公开(公告)日：2018-08-14

申请号：US15497964

申请日：2017-04-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu

IPC: H01L21/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/538

Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

公开(公告)号：US20160196990A1

公开(公告)日：2016-07-07

申请号：US15074110

申请日：2016-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Jung-Pang Huang ,  Shih-Kuang Chiu ,  Fu-Tang Huang

IPC: H01L21/56 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24153 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.

Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。

公开(公告)号：US20150072517A1

公开(公告)日：2015-03-12

申请号：US14487413

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Hung Lin ,  Meng-Tsung Lee ,  Sui-An Kao ,  Yi-Hsin Chen ,  Feng-Lung Chien

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/03903 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/0556 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2224/0347 ,  H01L2224/1161 ,  H01L2224/05552

Abstract: A fabrication method of a semiconductor structure includes providing a chip having at least an electrode pad, forming a titanium layer on the electrode pad, forming a dielectric layer on the chip and a portion of the titanium layer, forming a copper layer on the dielectric layer and the titanium layer, forming a conductive pillar on the copper layer corresponding in position to the titanium layer, and removing a portion of the copper layer that is not covered by the conductive pillar. When the portion of the copper layer is removed by etching, undercutting of the titanium layer is avoided since the titanium layer is covered by the dielectric layer, thereby providing an improved support for the conductive pillar to increase product reliability.

Abstract translation: 半导体结构的制造方法包括提供至少具有电极焊盘的芯片，在电极焊盘上形成钛层，在芯片上形成电介质层和钛层的一部分，在电介质层上形成铜层 和钛层，在与铜层相对应的铜层上形成导电柱，并除去未被导电柱覆盖的铜层的一部分。 当通过蚀刻去除铜层的部分时，由于钛层被电介质层覆盖，所以避免了钛层的底切，从而为导电柱提供改进的支撑以提高产品的可靠性。

公开(公告)号：US20140252603A1

公开(公告)日：2014-09-11

申请号：US14056230

申请日：2013-10-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Yi-Che Lai ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/1401 ,  H01L2224/1412 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.

Abstract translation: 提供一种半导体器件，包括：具有相对的第一和第二表面的衬底和穿过第一和第二表面的多个导电通孔; 绝缘层，形成在所述基板的所述第一表面上，并暴露所述导电通孔的端部; 以及在导电通孔的端部的周边形成在绝缘层上的缓冲层，从而提高产品的可靠性和良好的产率。

公开(公告)号：US10199331B2

公开(公告)日：2019-02-05

申请号：US15883808

申请日：2018-01-30

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Fu-Tang Huang

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31

Abstract: A method for fabricating an electronic package is provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.

公开(公告)号：US10192838B2

公开(公告)日：2019-01-29

申请号：US15411204

申请日：2017-01-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Lung Chuang ,  Po-Yi Wu ,  Meng-Tsung Lee ,  Yih-Jenn Jiang

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/31

Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.

公开(公告)号：US20170133337A1

公开(公告)日：2017-05-11

申请号：US15411204

申请日：2017-01-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Lung Chuang ,  Po-Yi Wu ,  Meng-Tsung Lee ,  Yih-Jenn Jiang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3157 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.

公开(公告)号：US20170077047A1

公开(公告)日：2017-03-16

申请号：US14983049

申请日：2015-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Meng-Tsung Lee ,  Fu-Tang Huang

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic device package and manufacturing method are provided, including steps of: providing a carrier having at least an electronic element and at least a package block disposed thereon, wherein the package block has a plurality of conductive posts bonded to the carrier; forming an encapsulant on the carrier for encapsulating the electronic element and the package block; and removing the carrier so as to expose the electronic element and the conductive posts from a surface of the encapsulant. As such, the invention dispenses with formation of through holes in the encapsulant for forming the conductive posts as in the prior art, thereby saving the fabrication cost.

Abstract translation: 提供了一种电子器件封装和制造方法，包括以下步骤：提供至少具有电子元件和至少设置在其上的封装块的载体，其中所述封装块具有结合到所述载体的多个导电柱; 在所述载体上形成密封剂以封装所述电子元件和所述封装块; 并移除载体，以使电子元件和导电柱从密封剂的表面露出。 因此，如现有技术那样，本发明省去了用于形成导电柱的密封剂中的通孔的形成，从而节省制造成本。

公开(公告)号：US20130341774A1

公开(公告)日：2013-12-26

申请号：US13628795

申请日：2012-09-27

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chiang-Cheng Chang ,  Meng-Tsung Lee ,  Shih-Kuang Chiu

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield.

Abstract translation: 提供一种半导体封装，包括：绝缘层; 嵌入绝缘层中的半导体元件; 嵌入在所述绝缘层中的粘合体，其中所述半导体元件的一部分嵌入所述粘合体中; 图案化金属层，其嵌入在所述粘合体中并电连接到所述半导体元件; 以及形成在绝缘层上并与图案化的金属层电连接的再分布结构。 通过将半导体元件嵌入到粘合体中，本发明可以将半导体元件可靠地固定在预定位置而没有任何位置偏差，从而提高产品产量。