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公开(公告)号:US11289398B2
公开(公告)日:2022-03-29
申请号:US16805869
申请日:2020-03-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Hui Wang , Der-Chyang Yeh , Shih-Peng Tai , Tsung-Shu Lin , Yi-Chung Huang
IPC: H01L23/367 , H01L23/13 , H01L23/00 , H01L23/498 , H01L25/065
Abstract: A package structure including a substrate, a semiconductor device, a heat spreader, and an adhesive layer is provided. The semiconductor device is bonded onto the substrate, wherein an angle θ is formed between one sidewall of the semiconductor device and one sidewall of the substrate, 0°
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公开(公告)号:US11195802B2
公开(公告)日:2021-12-07
申请号:US16893440
申请日:2020-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC: H01L23/552 , H01L21/76 , H01L23/538 , H01L23/00 , H01L23/488 , H01L21/768 , H01L23/31 , H01L21/56
Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号:US20210343619A1
公开(公告)日:2021-11-04
申请号:US17373250
申请日:2021-07-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wensen Hung , Tsung-Yu Chen , Tsung-Shu Lin , Chen-Hsiang Lao , Wen-Hsin Wei , Hsien-Pin Hu
IPC: H01L23/367 , H01L21/48 , H01L25/065 , H01L21/56 , H01L21/67 , H01L23/00 , H01L23/40 , H01L23/31 , H01L23/498
Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
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公开(公告)号:US20210305122A1
公开(公告)日:2021-09-30
申请号:US16835322
申请日:2020-03-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Chih Lai , Chien-Chia Chiu , Chen-Hua Yu , Der-Chyang Yeh , Cheng-Hsien Hsieh , Li-Han Hsu , Tsung-Shu Lin , Wei-Cheng Wu , Yu-Chen Hsu
IPC: H01L23/367 , H01L23/31 , H01L23/538 , H01L23/498 , H01L25/065 , H01L21/56 , H01L25/00 , H01L21/52
Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.
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公开(公告)号:US20210233833A1
公开(公告)日:2021-07-29
申请号:US17228018
申请日:2021-04-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Chang Ku , Hung-Chi Li , Tsung-Shu Lin , Tsung-Yu Chen , Wensen Hung
IPC: H01L23/427 , H01L21/48 , H01L25/00 , H01L25/065
Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.
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公开(公告)号:US20210098391A1
公开(公告)日:2021-04-01
申请号:US16893440
申请日:2020-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC: H01L23/552 , H01L23/00 , H01L23/488 , H01L23/538 , H01L23/31 , H01L21/56 , H01L21/768
Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号:US10756038B1
公开(公告)日:2020-08-25
申请号:US16281092
申请日:2019-02-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ming-Yen Chiu , Shou-Yi Wang , Tsung-Shu Lin
IPC: H01L23/00 , H01L23/522 , H01L23/31 , H01L21/56
Abstract: A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures. The second pad structure is disposed over and contacts the second vias, wherein a vertical projection of each of first pad structures overlaps with a vertical projection of the second pad structure, and an overall area of the vertical projections of the first pad structures is smaller than an area of the vertical projection of the second pad structure. The conductive terminal is disposed over and connects with the second pad structure.
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公开(公告)号:US20170005060A1
公开(公告)日:2017-01-05
申请号:US15268693
申请日:2016-09-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chang-Chia Huang , Tsung-Shu Lin , Ming-Da Cheng , Wen-Hsiung Lu , Bor-Rung Su
IPC: H01L23/00 , H01L21/56 , H01L23/482
CPC classification number: H01L24/16 , H01L21/28 , H01L21/302 , H01L21/565 , H01L21/76895 , H01L23/48 , H01L23/4824 , H01L23/498 , H01L23/538 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/056 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16238 , H01L2224/81191 , H01L2224/81815 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/00012 , H01L2924/014 , H01L2224/05552 , H01L2924/00
Abstract: The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.
Abstract translation: 本公开涉及集成芯片封装装置。 在一些实施例中,包装装置具有第一包装部件。 金属痕迹布置在第一包装部件的表面上。 金属痕迹有底切。 成型材料填充金属迹线的底切,并且具有倾斜的最外侧壁,其高度从金属迹线的顶表面下方的位置单调地降低到第一包装部件的表面。 焊料区域布置在金属迹线上方。
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公开(公告)号:US20250022825A1
公开(公告)日:2025-01-16
申请号:US18510523
申请日:2023-11-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sheng-Han Tsai , Tsung-Yu Chen , Hong-Yu Guo , Tsung-Shu Lin , Hsin-Yu Pan
IPC: H01L23/00 , H01L21/768 , H01L23/522 , H01L23/58
Abstract: In an embodiment, a method includes: forming active devices over a semiconductor substrate; forming an interconnect structure over the active devices, the interconnect structure comprising a first portion of a seal ring over the semiconductor substrate, the seal ring being electrically insulated from the active devices; forming a first passivation layer over the interconnect structure; forming a first metal pad and a second metal pad extending through the first passivation layer and over the interconnect structure, the first metal pad having a bowl shape, the second metal pad having a step shape; and depositing a second passivation layer over the first metal pad and the second metal pad.
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公开(公告)号:US20240234340A1
公开(公告)日:2024-07-11
申请号:US18151545
申请日:2023-01-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Che Chiang , Yuan Sheng Chiu , Hong-Yu Guo , Hsin-Yu Pan , Tsung-Shu Lin
CPC classification number: H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L25/105 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/80 , H01L24/81 , H01L24/92 , H01L2224/0401 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/0603 , H01L2224/06181 , H01L2224/06517 , H01L2224/08147 , H01L2224/13109 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16147 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2224/81191 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2224/9222 , H01L2924/0544 , H01L2924/05494
Abstract: An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.
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