公开(公告)号：US09812413B2

公开(公告)日：2017-11-07

申请号：US14994537

申请日：2016-01-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L29/06

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0549 ,  H01L2924/10156 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0231 ,  H01L2224/48

Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

公开(公告)号：US09704772B2

公开(公告)日：2017-07-11

申请号：US15008241

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  G06K9/00 ,  G01L19/14 ,  G06F21/32 ,  H01L21/02 ,  G01L19/00 ,  G01L19/06 ,  H01L23/525 ,  H01L21/60

CPC classification number: H01L23/3192 ,  G01L19/0061 ,  G01L19/06 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  G06K9/00006 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/525 ,  H01L2021/60022 ,  H01L2224/11 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K3/32

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

公开(公告)号：US09640405B2

公开(公告)日：2017-05-02

申请号：US14983401

申请日：2015-12-29

Applicant: XINTEC INC.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/768 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

公开(公告)号：US09570633B2

公开(公告)日：2017-02-14

申请号：US14570949

申请日：2014-12-15

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L35/34 ,  H01L35/02 ,  H01L23/31 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00

CPC classification number: H01L35/08 ,  G01J5/024 ,  G01J5/045 ,  G01J5/20 ,  H01L21/78 ,  H01L23/053 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/33 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/1876 ,  H01L35/02 ,  H01L35/10 ,  H01L35/34 ,  H01L2224/11

Abstract: A semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).

Abstract translation: 半导体封装包括基板，至少一个支撑件，盖板和板。 衬底具有至少一个光传感器或热传感器，第一表面和与第一表面相对的第二表面。 光传感器或热传感器设置在第一表面上。 第二表面具有露出光传感器（或热传感器）的开口。 支撑件设置在第一表面上。 盖子设置在支撑件上，使得盖子在光传感器（或热传感器）上方，以在盖和光传感器（或热传感器）之间形成第一空间。 板被放置在第二表面上以覆盖开口，使得在板和光传感器（或热传感器）之间形成第二空间。

公开(公告)号：US09190362B2

公开(公告)日：2015-11-17

申请号：US14325812

申请日：2014-07-08

Applicant: XINTEC INC.

Inventor： Wen-Cheng Chien ,  Wen-Ken Huang ,  Chien-Hung Liu ,  Joey Lai

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/562 ,  H01L24/05 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/02235 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：衬底，其上具有半导体器件和导电焊盘; 填充形成在所述衬底中的沟槽的绝缘体环，其中所述绝缘体环围绕所述导电焊盘下方的中间层; 以及设置在所述基板的背面下方并与导电焊盘电连接的导电层。

公开(公告)号：US08722463B2

公开(公告)日：2014-05-13

申请号：US13734796

申请日：2013-01-04

Applicant: Xintec Inc.

Inventor： Chien-Hung Liu

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract translation: 本发明涉及一种芯片封装，其包括：具有至少一个焊盘区域和至少一个器件区域的半导体衬底，其中半导体衬底在焊盘区域中包括多个重掺杂区域，以及两个重掺杂 区域绝对隔离; 设置在所述焊盘区域上方的多个导电焊盘结构; 设置在所述芯片封装的侧壁处的至少一个开口以暴露所述重掺杂区域; 以及设置在所述开口中以与所述重掺杂区域电接触的导电图案。

公开(公告)号：US20130127001A1

公开(公告)日：2013-05-23

申请号：US13674264

申请日：2012-11-12

Applicant: Xintec Inc.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/0232 ,  H01L25/167 ,  H01L27/14618 ,  H01L31/02325 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package is provided, including a silicon-containing substrate, a photo-sensor chip disposed on the silicon-containing substrate, a plurality of conductive lines electrically connected to the silicon-containing substrate and the photo-sensor chip, an encapsulating layer encapsulating the photo-sensor chip and the conductive lines, and a colloid lens disposed on the encapsulating layer. With the photo-sensor chip stacked on the silicon-containing substrate, a circuit board may have a reduced region that is occupied by the semiconductor package. A method of fabricating the semiconductor package is also provided.

Abstract translation: 提供了一种半导体封装件，包括含硅衬底，设置在含硅衬底上的光电传感器芯片，与该含硅衬底和光电传感器芯片电连接的多个导电线，封装层 光传感器芯片和导电线，以及设置在封装层上的胶体透镜。 利用光电传感器芯片堆叠在含硅衬底上，电路板可以具有被半导体封装占据的减小的区域。 还提供了制造半导体封装的方法。

公开(公告)号：US10157875B2

公开(公告)日：2018-12-18

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L27/146 ,  H01L25/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

公开(公告)号：US09831185B2

公开(公告)日：2017-11-28

申请号：US15139276

申请日：2016-04-26

Applicant: XINTEC INC.

Inventor： Shih-Yi Lee ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Ho-Yin Yiu

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/78 ,  H01L21/683 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

Abstract: A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.

公开(公告)号：US09780050B2

公开(公告)日：2017-10-03

申请号：US15340909

申请日：2016-11-01

Applicant: XINTEC INC.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/768 ,  H01L21/304 ,  H01L23/498 ,  H01L21/56 ,  H01L23/48 ,  H01L27/146

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.