公开(公告)号：US11310904B2

公开(公告)日：2022-04-19

申请号：US16663366

申请日：2019-10-25

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Po-Han Lee ,  Wei-Ming Chien

IPC: H05K1/02 ,  H05K1/03 ,  H01L23/00

Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

公开(公告)号：US09780251B2

公开(公告)日：2017-10-03

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/18 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09613919B2

公开(公告)日：2017-04-04

申请号：US14958672

申请日：2015-12-03

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Po-Han Lee ,  Wei-Ming Chien

IPC: H01L23/00 ,  B81C3/00 ,  H01L23/31

CPC classification number: H01L24/02 ,  B81C3/00 ,  H01L23/3114 ,  H01L23/315 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/12041 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/81

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the first surface of the substrate and includes a conducting pad structure. A first opening penetrates the substrate and exposes a surface of the conducting pad structure. A second opening is communication with the first opening and penetrates the conducting pad structure. A redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the conducting pad structure and is filled into the second opening. A method for forming the chip package is also provided.

公开(公告)号：US09269837B2

公开(公告)日：2016-02-23

申请号：US14682888

申请日：2015-04-09

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Po-Han Lee

IPC: H01L23/00 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

Abstract translation: 芯片封装包括半导体芯片，内部间隔件，空腔，导电部分和焊球。 半导体芯片至少具有电子部件，并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

公开(公告)号：US09196571B2

公开(公告)日：2015-11-24

申请号：US14592840

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Po-Han Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/538 ,  H01L21/784 ,  H01L23/31 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/481 ,  H01L21/481 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

Abstract translation: 提供了一种芯片器件封装及其制造方法。 芯片器件封装包括具有第一表面和相对的第二表面的半导体衬底。 凹部与半导体衬底的侧壁相邻地设置，从半导体衬底的第一表面延伸到半导体衬底的至少第二表面。 保护层设置在半导体衬底的第一表面和凹部中。 在半导体衬底的第一表面上设置通孔。 与保护层的材料不同的缓冲材料设置在通孔中并被保护层覆盖。

公开(公告)号：US11355659B2

公开(公告)日：2022-06-07

申请号：US17075544

申请日：2020-10-20

Applicant: XINTEC INC.

Inventor： Po-Han Lee ,  Chia-Ming Cheng ,  Wei-Ming Chien

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/02 ,  H01L31/0216

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

公开(公告)号：US10153237B2

公开(公告)日：2018-12-11

申请号：US15461334

申请日：2017-03-16

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Chia-Sheng Lin ,  Po-Han Lee ,  Wei-Luen Suen

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L23/31

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

公开(公告)号：US09947716B2

公开(公告)日：2018-04-17

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chien-Min Lin

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US09875912B2

公开(公告)日：2018-01-23

申请号：US15358098

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Hsiao-Lan Yeh ,  Chia-Sheng Lin ,  Yi-Ming Chang ,  Po-Han Lee ,  Hui-Hsien Wu ,  Jyun-Liang Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  G06K9/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  G06K9/0004 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/16225

Abstract: A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.

公开(公告)号：US09406818B2

公开(公告)日：2016-08-02

申请号：US14971395

申请日：2015-12-16

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Po-Han Lee

IPC: H01L23/00 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.

Abstract translation: 制造芯片封装的方法包括提供具有多个半导体芯片的半导体晶片。 在半导体晶片上形成有外隔离物和多个内隔离物。 保护盖形成并设置在外隔离件和内间隔件上。 从其下表面在每个半导体芯片上形成多个空腔，以露出设置在半导体芯片的上表面上的导电焊盘。 形成多个导电部分，并填充每个空腔并电连接到每个导电焊盘。 多个焊球设置在下表面并电连接到每个导电部分。 半导体芯片通过沿着每个半导体芯片之间的多个切割线进行切割来分离。