公开(公告)号：US20240329329A1

公开(公告)日：2024-10-03

申请号：US18129765

申请日：2023-03-31

Applicant: XILINX, INC.

Inventor： Gamal REFAI-AHMED ,  Chuan Xie ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Nagadeven Karunakaran ,  Ferdinand F. Fernandez

IPC: G02B6/38 ,  G02B6/42

CPC classification number: G02B6/3849 ,  G02B6/381 ,  G02B6/4295

Abstract: A method of fabricating a chip package is provided, and a chip package fabricated using the same are provided. The method includes connecting a photonic die to a substrate of the chip package and attaching a protection apparatus to the substrate. The method also includes attaching a photonic connector to the photonic die. At least a portion of the photonic connector is disposed inside a housing of the protection apparatus. A fabrication process is performed on the chip package while the photonic connector is inside the housing. After processing, the photonic connector is removed from the housing.

公开(公告)号：US11107770B1

公开(公告)日：2021-08-31

申请号：US16454629

申请日：2019-06-27

Applicant: XILINX, INC.

Inventor： Suresh Ramalingam ,  Kun-Yung Chang ,  Yohan Frans ,  Chuan Xie ,  Mayank Raj

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/49 ,  H01L25/18 ,  G02B6/42 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

Abstract: An improved chip package, and methods for fabricating the same are provided that utilize two tier packaging of an optical die and another die commonly disposed over a substrate. In one example, a chip package is provided that includes an optical die, a core die, and an electrical/optical interface die are all disposed over a common substrate. In one example, a first routing region is provided between the core and electrical/optical interface dies, a second routing region is provided between the electrical/optical interface die and the optical dies, and a third routing region is disposed between the substrate and the core and electrical/optical interface dies.

公开(公告)号：US20180358280A1

公开(公告)日：2018-12-13

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US10147664B2

公开(公告)日：2018-12-04

申请号：US15495720

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Daniel Elftmann ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H05K1/18 ,  H01L23/433 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

公开(公告)号：US20180308783A1

公开(公告)日：2018-10-25

申请号：US15495720

申请日：2017-04-24

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Daniel Elftmann ,  Brian D. Philofsky ,  Anthony Torza

IPC: H01L23/367 ,  H05K1/18 ,  H01L23/433 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3672 ,  H01L23/3736 ,  H01L23/433 ,  H01L23/4338 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/72 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29293 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32221 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/0665 ,  H01L2924/01006

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

公开(公告)号：US10038259B2

公开(公告)日：2018-07-31

申请号：US14174697

申请日：2014-02-06

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Sarajuddin Niazi ,  Raymond E. Anderson ,  Suresh Ramalingam

IPC: H05K1/11 ,  H05K1/14 ,  H01R12/71 ,  H01R43/02 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

公开(公告)号：US09812374B1

公开(公告)日：2017-11-07

申请号：US15466495

申请日：2017-03-22

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Brian D. Philofsky

IPC: H01L23/12 ,  H01L21/00 ,  H05K7/20 ,  H01L23/367 ,  H01L23/427 ,  H01L25/065 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L23/10 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/427 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/292 ,  H01L2224/29224 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a device with a textured surface having multiple grooves in an otherwise relatively flat surface. The textured surface of the heat management device is designed, in conjunction with a thermal interface material (TIM), to push gas bubbles out of the flat areas such that the gas bubbles are trapped in the grooves or driven out of the interface between the device and the TIM altogether. The area of the grooves is small relative to the ungrooved areas (i.e., the flat areas), such that when the gas bubbles are trapped in the grooved areas, the ungrooved areas work even better for heat transfer. With the area of the regions for the flat portions being substantially greater than the area of the regions for the grooves, the textured heat management device is designed to lower thermal resistance, increase thermal conductivity, and increase heat transfer from one or more IC dies to a heat sink assembly in an IC package.

公开(公告)号：US09147661B1

公开(公告)日：2015-09-29

申请号：US14171517

申请日：2014-02-03

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92135 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00015 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2224/32507 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2224/1147 ,  H01L2224/034 ,  H01L2224/11849

Abstract: Implementations described herein generally relate to chip packaging, and in particular, to solder bump structures for a semiconductor device and methods of fabricating the same. In one implementation, a solder bump assembly is provided. The solder bump assembly comprises a conductive bond pad formed on a substrate. A conductive pillar is formed on the conductive bond pad. A plating layer is formed on the conductive pillar, wherein the plating layer comprises copper and nickel. A solder bump is formed on the plating layer in electrical communication with the plating layer. The plating layer may be a bi-layer structure comprising a nickel layer formed on the conductive pillar and a copper layer formed on the nickel layer in electrical communication with the solder bump. The plating layer may be a copper-nickel alloy.

Abstract translation: 本文描述的实施方式通常涉及芯片封装，特别涉及用于半导体器件的焊料凸块结构及其制造方法。 在一个实施方案中，提供了焊料凸块组件。 焊料凸块组件包括形成在衬底上的导电接合焊盘。 在导电接合焊盘上形成导电柱。 在导电柱上形成镀层，其中镀层包括铜和镍。 在镀层上形成与镀层电连通的焊料凸块。 镀层可以是包括形成在导电柱上的镍层和形成在镍层上与焊料凸块电连通的铜层的双层结构。 镀层可以是铜镍合金。

公开(公告)号：US20250096136A1

公开(公告)日：2025-03-20

申请号：US18471114

申请日：2023-09-20

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Divya Madapusi Srinivas Prasad ,  Gabriel H. Loh ,  Richard Schultz ,  Jeffrey Richard Rearick ,  Shidhartha Das ,  Suresh Ramalingam

IPC: H01L23/528 ,  H01L23/48

Abstract: A disclosed semiconductor device includes (1) a silicon stack comprising a front-side Back-End-of-Line (BEOL) stack and a back side BEOL stack, the front-side BEOL stack comprising a plurality of signal routes and the back-side BEOL stack comprising a plurality of power delivery routes, and (2) a plurality of auxiliary power paths formed within the front-side BEOL stack and electrically coupled to the plurality of power delivery routes of the back-side BEOL stack via a plurality of programmable switches, the plurality of power delivery routes, the plurality of programmable switches, and the plurality of auxiliary power paths forming a programmable power delivery network (PDN). Various other apparatuses, systems, and methods of operation are also disclosed.

公开(公告)号：US11476556B1

公开(公告)日：2022-10-18

申请号：US17102149

申请日：2020-11-23

Applicant: XILINX, INC.

Inventor： Mohsen H. Mardi ,  Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Volker Aue

IPC: H01Q1/00 ,  H01Q1/02 ,  F28F1/42 ,  F28F1/00 ,  H01Q1/42

Abstract: A heat exchanger and an antenna assembly having the same are described herein that enable a compact antenna design with good thermal management. In one example, a heat exchanger is provided that includes tube-shaped body. A main cooling volume is formed between the top and bottom surfaces proximate to the outside wall. The main cooling volume has an inlet formed through the top surface and an outlet formed through the bottom surface. A return volume is formed adjacent the inside diameter wall and is circumscribed by the main cooling volume. The return volume has an outlet formed through the top surface and an inlet formed through the bottom surface. One or more exterior fins are coupled to an exterior side of the outside wall. A plurality of fins extend into the main cooling volume. A plurality of inner fins extend into a passage from the inside diameter wall.