公开(公告)号：US08896136B2

公开(公告)日：2014-11-25

申请号：US12827563

申请日：2010-06-30

申请人： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/544 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L21/76 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/683

CPC分类号： H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

摘要： In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

摘要翻译： 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

公开(公告)号：US08846499B2

公开(公告)日：2014-09-30

申请号：US12858211

申请日：2010-08-17

申请人： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/30

CPC分类号： G07F17/3213 ,  B32B17/10 ,  B32B37/1207 ,  B32B37/182 ,  B32B37/185 ,  B32B2457/14 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

摘要： A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.

摘要翻译： 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。 在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

公开(公告)号：US20120238057A1

公开(公告)日：2012-09-20

申请号：US13488188

申请日：2012-06-04

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US20110316147A1

公开(公告)日：2011-12-29

申请号：US12823851

申请日：2010-06-25

申请人： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/488

CPC分类号： H01L21/76885 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4007 ,  H05K2203/016 ,  H05K2203/025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/16145 ,  H01L2924/00012

摘要： A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

摘要翻译： 一种装置包括：插入件，其包括基板; 以及衬底上的至少一个电介质层。 多个穿通基板通孔（TSV）穿透基板。 第一金属凸块在至少一个电介质层中并电耦合到多个TSV。 第二金属凸块在至少一个电介质层的上方。 模具嵌入在至少一个电介质层中并结合到第一金属凸块。

公开(公告)号：US08759150B2

公开(公告)日：2014-06-24

申请号：US13488188

申请日：2012-06-04

申请人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

发明人： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC分类号： H01L21/50

CPC分类号： H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

摘要翻译： 一种方法包括提供包括衬底的中介层晶片，以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔（TSV）。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后，在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。

公开(公告)号：US08426961B2

公开(公告)日：2013-04-23

申请号：US12823851

申请日：2010-06-25

申请人： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Ying-Ching Shih ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L21/76885 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4007 ,  H05K2203/016 ,  H05K2203/025 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/16145 ,  H01L2924/00012

摘要： A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

摘要翻译： 一种装置包括：插入件，其包括基板; 以及衬底上的至少一个电介质层。 多个穿通基板通孔（TSV）穿透基板。 第一金属凸块在至少一个电介质层中并电耦合到多个TSV。 第二金属凸块在至少一个电介质层的上方。 模具嵌入在至少一个电介质层中并结合到第一金属凸块。

公开(公告)号：US20120040500A1

公开(公告)日：2012-02-16

申请号：US12857245

申请日：2010-08-16

申请人： Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/67126 ,  H01L23/3121 ,  H01L24/94 ,  H01L2224/16145 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

摘要： A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer.

摘要翻译： 公开了一种用于半导体模制室的系统和方法。 一个实施例包括顶部模制部分和底部模制部分，其在其间放置半导体晶片的它们之间形成空腔。 半导体模制室具有第一组真空管，其保持和固定半导体晶片的位置，以及第二组真空管，其抽空外部环境气体的空腔。 然后可以将密封剂放置在半导体晶片上以便封装半导体晶片。

公开(公告)号：US08716867B2

公开(公告)日：2014-05-06

申请号：US12778867

申请日：2010-05-12

申请人： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Francis Ko ,  Chi-Chun Hsieh ,  Shang-Yun Hou ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B41F33/00

CPC分类号： H01L23/5384 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49883 ,  H01L23/525 ,  H01L23/5328 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

摘要翻译： 形成器件的方法包括在电介质片上印刷导电图案以形成预先印墨的片材，以及将预印墨片材粘合到基片的一侧上。 导电特征包括从衬底的第一主侧延伸到与第一主侧相对的衬底的第二主侧的贯通衬底。 然后施加导电膏以将导电图案电耦合到衬底中的导电特征。

公开(公告)号：US08674513B2

公开(公告)日：2014-03-18

申请号：US12779734

申请日：2010-05-13

申请人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Tsang-Jiuh Wu

发明人： Chen-Hua Yu ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Tsang-Jiuh Wu

IPC分类号： H01L23/522

CPC分类号： H01L21/76895 ,  H01L21/563 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5283 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00

摘要： A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.

摘要翻译： 提供了一种与集成电路一起使用的装置。 该器件包括具有通过其形成的贯通基板通孔的基板。 电介质层形成在衬底的至少一侧上，并且在电介质层内形成金属化层。 最靠近贯穿衬底通孔的第一金属化层大于一个或多个上覆的金属化层。 在一个实施例中，顶部金属化层大于一个或多个下面的金属化层。 集成电路管芯可以在衬底的一侧或两侧附着到衬底，并且衬底的任一侧可以附接到另一个衬底，例如印刷电路板，高密度互连，封装衬底，有机 基板，层叠基板等。

公开(公告)号：US20120313247A1

公开(公告)日：2012-12-13

申请号：US13157137

申请日：2011-06-09

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Wen-Chih Chiou ,  Fang Wen Tsai ,  Chen-Yu Tsai

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/0217 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2224/05552

摘要： A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

摘要翻译： 公开了一种制造硅通孔的系统和方法。 一个实施例包括用从衬底突出的衬垫形成通孔硅通孔。 钝化层形成在衬底和穿通硅通孔之上，钝化层和衬垫从通硅通孔的侧壁凹陷。 然后可以将导电材料形成为与通孔硅通孔的两个侧壁和顶表面接触。