公开(公告)号：US20180166392A1

公开(公告)日：2018-06-14

申请号：US15825778

申请日：2017-11-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI

IPC: H01L23/532 ,  H01L23/485 ,  H01L27/01 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L23/53295 ,  H01L21/28 ,  H01L23/485 ,  H01L23/532 ,  H01L27/016 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/08 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator over the first conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the first conductor, and a side surface of the third insulator; a fifth insulator in contact with a top surface of the oxide and a side surface of the fourth insulator; and a second conductor in contact with the top surface of the oxide and the fifth insulator. The level of the top surface of the fourth insulator is higher than the level of the top surface of the fifth insulator.

公开(公告)号：US09972606B2

公开(公告)日：2018-05-15

申请号：US15604803

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L29/41 ,  H01L23/495 ,  H01L23/482

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L24/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/50 ,  H01L29/40 ,  H01L29/41 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/50 ,  H01L2224/73261 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06579 ,  H01L2924/15311

Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

公开(公告)号：US09960185B2

公开(公告)日：2018-05-01

申请号：US14654329

申请日：2014-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiangyong Kong ,  Fengjuan Liu

IPC: H01L23/48 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/41 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/49 ,  H01L51/52 ,  H01L51/56 ,  H01L21/02

CPC classification number: H01L27/1218 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/78636 ,  H01L51/5206 ,  H01L51/5221 ,  H01L51/56 ,  H01L2251/301 ,  H01L2251/558

Abstract: A base and a manufacturing method thereof and a display device are provided, so that a problem of faultage of an insulating layer when forming the insulating layer on an aluminum electrode of a substrate is solved. The base includes an aluminum electrode in a first setting pattern on a substrate, and an aluminum oxide layer or an aluminum nitride layer (3) in a second setting pattern provided in a same layer with the aluminum electrode. The first setting pattern and the second setting pattern are complementary to each other.

公开(公告)号：US09929245B2

公开(公告)日：2018-03-27

申请号：US15401171

申请日：2017-01-09

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Chia-Wen Liu ,  Wei-Hao Wu ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/778 ,  H01L29/78 ,  H01L21/8228 ,  H01L29/06 ,  H01L29/786 ,  H01L27/092 ,  H01L29/66 ,  H01L29/41

CPC classification number: H01L29/4908 ,  H01L21/28008 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823487 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0676 ,  H01L29/41 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2029/42388

Abstract: Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.

公开(公告)号：US20180026109A1

公开(公告)日：2018-01-25

申请号：US15601180

申请日：2017-05-22

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Akitaka SOENO

IPC: H01L29/41

CPC classification number: H01L29/41 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/4334 ,  H01L2224/33

Abstract: A semiconductor device may include a semiconductor substrate; a first metal film covering a surface of the semiconductor substrate; a protection film covering a peripheral portion of a surface of the first metal film; and a second metal film covering a range extending across a center portion of the surface of the first metal film and a surface of the protection film, wherein a recess may be provided in the surface of the protection film, and a part of the second metal film may be in contact with an inner surface of the recess.

公开(公告)号：US20180012818A1

公开(公告)日：2018-01-11

申请号：US15714099

申请日：2017-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/31 ,  H01L29/40 ,  H01L23/00 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/482 ,  H01L23/532

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

公开(公告)号：US09842921B2

公开(公告)日：2017-12-12

申请号：US14205811

申请日：2014-03-12

Applicant: Wisconsin Alumni Research Foundation

Inventor： Mark A. Eriksson ,  John King Gamble ,  Daniel R. Ward ,  Susan Nan Coppersmith ,  Mark G. Friesen

IPC: B82Y10/00 ,  H01L29/778 ,  H01L29/423 ,  H01L29/76 ,  H01L29/41 ,  H01L29/12 ,  H01L27/088 ,  H01L29/165 ,  H01L29/16

CPC classification number: H01L29/7782 ,  H01L27/088 ,  H01L29/127 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/41 ,  H01L29/413 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/7613 ,  H01L29/778

Abstract: A quantum semiconductor device is provided. The quantum semiconductor device includes a quantum heterostructure, a dielectric layer, and an electrode. The quantum heterostructure includes a quantum well layer that includes a first 2DEG region, a second 2DEG region, and a third 2DEG region. A first tunnel barrier exists between the first 2DEG region and the second 2DEG region. A second tunnel barrier exists between the second 2DEG region and the third 2DEG region. A third tunnel barrier exists either between the first 2DEG region and the third 2DEG region. The dielectric layer is formed on the quantum heterostructure. The electrode is formed on the dielectric layer directly above the first tunnel barrier.

公开(公告)号：US09773716B2

公开(公告)日：2017-09-26

申请号：US15146012

申请日：2016-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Liao ,  Han-Wei Yang ,  Chen-Chung Lai ,  Kang-Min Kuo ,  Bor-Zen Tien

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/528 ,  H01L29/40 ,  H01L23/29 ,  H01L23/532

CPC classification number: H01L23/3171 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/564 ,  H01L29/401 ,  H01L29/41 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is disclosed in some embodiments. The device includes a substrate, and a layer disposed over the substrate. The layer includes an opening extending through the layer. A plurality of bar or pillar structures or a tapered region are arranged in a peripheral portion of the opening and laterally surround a central portion of the opening. A metal body extends through the central portion of the opening.

公开(公告)号：US20170271309A1

公开(公告)日：2017-09-21

申请号：US15604803

申请日：2017-05-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L24/50 ,  H01L25/00 ,  H01L25/065 ,  H01L25/50 ,  H01L29/40 ,  H01L29/41 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/50 ,  H01L2224/73261 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06579 ,  H01L2924/15311

Abstract: A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

公开(公告)号：US20170110549A1

公开(公告)日：2017-04-20

申请号：US14887927

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/417 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.