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    Chip package with multiple spacers and method for forming the same
    221.
    发明授权
    Chip package with multiple spacers and method for forming the same 有权
    具有多个间隔物的芯片封装及其形成方法

    公开(公告)号：US08748926B2

    公开(公告)日：2014-06-10

    申请号：US13720649

    申请日：2012-12-19

    Applicant: Xintec Inc.

    Inventor： Kuo-Hua Liu ,  Yi-Ming Chang ,  Hsi-Chien Lin

    IPC: H01L33/00 ,  H01L21/00

    CPC classification number: H01L21/78 ,  H01L21/50 ,  H01L21/561 ,  H01L23/10 ,  H01L23/48 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 μm; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

    Abstract translation: 芯片封装包括：具有第一和第二表面的衬底; 形成在基板上或设置在基板上的器件区域; 设置在所述第一表面上的电介质层; 至少一个导电焊盘，其布置在所述电介质层中并电连接到所述器件区域; 设置在所述电介质层上的平面层，其中所述平面层的上表面与所述导电焊盘之间的垂直距离大于约2μm; 设置在所述第一表面上的透明基板; 设置在所述透明基板和所述平面层之间的第一间隔层; 以及第二间隔层，其设置在所述透明基板和所述基板之间并且延伸到所述电介质层的与所述导电焊盘接触的开口中，其中所述第二间隔层和所述导电焊盘之间基本上没有间隙。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    224.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
    芯片包装及其形成方法

    公开(公告)号：US20130341747A1

    公开(公告)日：2013-12-26

    申请号：US13921999

    申请日：2013-06-19

    Applicant: XINTEC INC.

    Inventor： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Shih-Chin CHEN

    IPC: H01L31/0232 ,  H01L31/02

    CPC classification number: H01L31/0232 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/02 ,  H01L31/02327 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

    Abstract translation: 本发明的实施例提供一种芯片封装，其包括：芯片，包括：具有第一表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 以及在所述第一表面和所述器件区域上的多个微透镜; 设置在所述芯片上的盖基板，其中所述盖基板为透明基板; 设置在所述芯片和所述覆盖基板之间的间隔层，其中所述间隔层，所述芯片和所述覆盖基板一起围绕所述器件区域中的空腔; 以及在所述盖基板上和所述空腔中的至少一个主透镜，其中所述主透镜的宽度大于每个所述微透镜的宽度。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    225.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20130328147A1

    公开(公告)日：2013-12-12

    申请号：US13912792

    申请日：2013-06-07

    Applicant: XINTEC INC.

    Inventor： Yen-Shih HO ,  Ying-Nan WEN ,  Tsang-Yu LIU

    IPC: H01L31/02 ,  H01L31/0232

    CPC classification number: H01L27/14687 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L31/02002 ,  H01L31/0232 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a device region disposed in the semiconductor substrate; a dielectric layer disposed on the first surface of the semiconductor substrate; a conducting pad structure disposed in the dielectric layer and electrically connected to the device region, a carrier substrate disposed on the dielectric layer; and a conducting structure disposed in a bottom surface of the carrier substrate and electrically contacting with the conducting pad structure.

    Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 设置在所述半导体衬底中的器件区域; 设置在所述半导体衬底的第一表面上的电介质层; 布置在所述电介质层中并电连接到所述器件区的导电焊盘结构，设置在所述电介质层上的载体衬底; 以及设置在所述载体基板的底表面中并与所述导电焊盘结构电接触的导电结构。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    226.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 审中-公开
    芯片包装及其形成方法

    公开(公告)号：US20130316494A1

    公开(公告)日：2013-11-28

    申请号：US13956487

    申请日：2013-08-01

    Applicant: XINTEC INC.

    Inventor： Chia-Ming CHENG

    IPC: H01L23/00

    CPC classification number: H01L24/85 ,  B81B7/007 ,  B81C2203/0118 ,  H01L24/45 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/45099

    Abstract: An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures.

    Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的基板; 位于衬底上表面的钝化层; 多个导电焊盘结构，其布置在所述衬底的上表面上方，其中所述导电焊盘结构的上表面的至少部分被暴露; 从所述基板的上表面向下表面延伸的多个开口; 以及位于所述开口之间且分别与所述基板连接的多个可移动块，其中每个所述可移动块与所述导电垫结构之一电连接。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    228.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20130153933A1

    公开(公告)日：2013-06-20

    申请号：US13720627

    申请日：2012-12-19

    Applicant: XINTEC INC.

    Inventor： Po-Han LEE ,  Chien-Hung LIU

    IPC: H01L31/12 ,  H01L31/18

    CPC classification number: H01L31/12 ,  H01L31/1876

    Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a sensor region formed in the semiconductor substrate; a light emitting device disposed on the second surface of the semiconductor substrate; at least one first conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the sensor region; at least one second conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the light emitting device; and an insulating layer located on the semiconductor substrate to electrically insulate the semiconductor substrate from the at least one first conducting bump and the at least one second conducting bump.

    Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的传感器区域; 设置在所述半导体衬底的第二表面上的发光器件; 至少一个第一导电凸块，设置在所述半导体衬底的所述第一表面上并电连接到所述传感器区域; 设置在所述半导体衬底的所述第一表面上并电连接到所述发光器件的至少一个第二导电凸块; 以及绝缘层，其位于所述半导体衬底上以将所述半导体衬底与所述至少一个第一导电凸块和所述至少一个第二导电凸块电绝缘。

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