公开(公告)号：US09953972B2

公开(公告)日：2018-04-24

申请号：US15470866

申请日：2017-03-27

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  H01L21/762 ,  H01L27/108 ,  H01L21/8234 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0688 ,  H01L21/76254 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/585 ,  H01L25/0657 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/10802 ,  H01L27/10897 ,  H01L28/00 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.

公开(公告)号：US09953870B2

公开(公告)日：2018-04-24

申请号：US15488514

申请日：2017-04-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L21/77 ,  H01L29/66 ,  H01L27/10 ,  H01L23/40 ,  H01L23/00 ,  H01L23/31 ,  H01L27/02 ,  B82Y10/00 ,  H01L21/84 ,  H01L23/528 ,  H01L21/683 ,  H01L21/762 ,  H01L27/06 ,  H01L29/78 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/10 ,  G11C16/04 ,  H01L23/36 ,  H01L23/367 ,  H01L27/088

CPC classification number: H01L21/77 ,  B82Y10/00 ,  G11C16/0408 ,  G11C16/0483 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4012 ,  H01L23/5286 ,  H01L24/01 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/1033 ,  H01L29/66257 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/6835 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.

公开(公告)号：US20170294415A1

公开(公告)日：2017-10-12

申请号：US15632325

申请日：2017-06-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L25/065 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L23/544 ,  H01L25/0652 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593

Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.

公开(公告)号：US20170287844A1

公开(公告)日：2017-10-05

申请号：US15622124

申请日：2017-06-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/544 ,  H01L27/088 ,  H01L23/34 ,  H01L27/11551 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L21/74

CPC classification number: H01L29/66704 ,  H01L21/743 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/34 ,  H01L23/481 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/1203 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/786 ,  H01L29/808 ,  H01L45/04 ,  H01L45/06 ,  H01L45/146 ,  H01L45/16 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.

公开(公告)号：US20170186770A1

公开(公告)日：2017-06-29

申请号：US15460230

申请日：2017-03-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman ,  Israel Beinglass

IPC: H01L27/11582 ,  H01L29/16 ,  H01L27/11575 ,  H01L29/04 ,  H01L27/11573 ,  H01L27/24

CPC classification number: H01L27/11582 ,  B82Y10/00 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/00 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/2436 ,  H01L27/249 ,  H01L28/00 ,  H01L29/04 ,  H01L29/0673 ,  H01L29/66272 ,  H01L29/66439 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/775 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2221/68368 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599

Abstract: A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.

公开(公告)号：US20170092541A1

公开(公告)日：2017-03-30

申请号：US15201430

申请日：2016-07-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L23/367 ,  H01L27/22 ,  H01L27/24 ,  H01L21/762 ,  H01L27/108

CPC classification number: H01L21/8221 ,  H01L21/76254 ,  H01L23/367 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/226 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/42392 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A 3D semiconductor device including: a first structure including first single crystal transistors; a second structure including second single crystal transistors, the second structure overlaying the first single crystal transistors, where at least one of the second single crystal transistors is at least partially self-aligned to at least one of the first single crystal transistors; and at least one thermal conducting path from at least one of the first single crystal transistors and second single crystal transistors to an external surface of the device.

公开(公告)号：US09412645B1

公开(公告)日：2016-08-09

申请号：US14200061

申请日：2014-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H03K19/094 ,  H01L21/768 ,  H01L23/525

CPC classification number: H01L27/1128 ,  G06F17/505 ,  G06F17/5068 ,  H01L21/768 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1305 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/1778 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for fabricating semiconductor devices, including: providing a CMOS fabric and metal layers, the metal layers including a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer, the metal layers providing interconnection for the CMOS fabric, and constructing mask defined connections between the third metal layer and the fourth metal layer, the mask defined connections are substantially similar to antifuse programmed connections of a programmed antifuse programmable device, where the antifuse programmable device is a 3D antifuse programmable device including antifuses and antifuse programming transistors, where the antifuse programming transistors overlay the antifuses, and where the antifuse programming transistors include a monocrystalline channel.

Abstract translation: 一种制造半导体器件的方法，包括：提供CMOS结构和金属层，所述金属层包括第一金属层，第二金属层，第三金属层和第四金属层，所述金属层为CMOS提供互连 织物，并且在第三金属层和第四金属层之间构造掩模限定的连接，掩模限定的连接基本上类似于编程反熔丝可编程器件的反熔丝编程连接，其中反熔丝可编程器件是包括反熔丝的3D反熔丝可编程器件， 反熔丝编程晶体管，其中反熔丝编程晶体管覆盖反熔丝，并且其中反熔丝编程晶体管包括单晶通道。

公开(公告)号：US20150123072A1

公开(公告)日：2015-05-07

申请号：US14555494

申请日：2014-11-26

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L27/108

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

Abstract translation: 一种器件，包括：包括第一晶体管的第一层和包括第二晶体管的第二层，其中所述第一晶体管中的至少一个与所述第二晶体管之一自对准，其中所述第二晶体管是水平取向的晶体管，并且其中 第二层包括多个电阻随机存取存储器（RRAM）单元，该存储单元包括第二晶体管。

公开(公告)号：US08921970B1

公开(公告)日：2014-12-30

申请号：US14198041

申请日：2014-03-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; where the second layer includes a through layer via with a diameter of less than 150 nm, and where at least one of the second transistors includes a back-bias structure.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 第二层，包括多个第二晶体管，所述第二层覆盖所述至少一个金属层; 其中第二层包括具有小于150nm的直径的贯穿层通孔，并且其中至少一个第二晶体管包括背偏置结构。

公开(公告)号：US08846463B1

公开(公告)日：2014-09-30

申请号：US13902606

申请日：2013-05-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L21/84 ,  H01L21/8232

CPC classification number: H01L23/4827 ,  H01L21/268 ,  H01L21/302 ,  H01L21/76232 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/1203 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/01066 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method to construct a semiconductor device, the method including: forming a first mono-crystallized semiconductor layer; forming a second mono-crystallized semiconductor layer including mono-crystallized semiconductor transistors; where the second mono-crystallized semiconductor layer overlays the first mono-crystallized semiconductor layer, where the first mono-crystallized semiconductor layer includes an alignment mark and the transistors are aligned to the alignment mark, and where the first mono-crystallized semiconductor layer includes logic circuits, and connecting the logic circuits to an external device using input/output (I/O) circuits, where the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Abstract translation: 一种构造半导体器件的方法，所述方法包括：形成第一单结晶半导体层; 形成包括单结晶半导体晶体管的第二单结晶半导体层; 其中所述第二单结晶半导体层覆盖所述第一单结晶半导体层，其中所述第一单结晶半导体层包括对准标记，并且所述晶体管与所述对准标记对准，并且其中所述第一单结晶半导体层包括逻辑 电路，并且使用输入/输出（I / O）电路将逻辑电路连接到外部设备，其中输入/输出（I / O）电路构造在第二单结晶半导体层上。