公开(公告)号：US09334158B2

公开(公告)日：2016-05-10

申请号：US13900081

申请日：2013-05-22

Applicant: XINTEC INC.

Inventor： Yu-Ting Huang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu

IPC: H01L23/48 ,  B81B7/00 ,  H01L21/64 ,  H01L23/498 ,  H01L23/525 ,  H01L23/00

CPC classification number: B81B7/0077 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/64 ,  H01L23/481 ,  H01L23/498 ,  H01L23/525 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06182 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，包括：第一半导体衬底; 设置在所述第一半导体衬底上的第二半导体衬底，其中所述第二半导体衬底包括下半导体层，上半导体层和位于所述下半导体层和所述上半导体层之间的绝缘层，以及所述下半导体 层与第一半导体衬底上的至少焊盘电接触; 信号导通结构，设置在所述第一半导体衬底的下表面上，其中所述信号导电结构电连接到所述第一半导体衬底上的信号焊盘; 以及导电层，其设置在所述第二半导体衬底的所述上半导体层上并与所述下半导体层的与所述第一半导体衬底上的所述至少一个焊盘电接触的部分电接触。

公开(公告)号：US09305843B2

公开(公告)日：2016-04-05

申请号：US14596185

申请日：2015-01-13

Applicant: XINTEC INC.

Inventor： Bing-Siang Chen ,  Chien-Hui Chen ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip, wherein a side surface of the second chip is a chemically-etched surface; and a bonding bulk disposed between the first chip and the second chip such that the first chip and the second chip are bonded with each other.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一芯片; 设置在所述第一芯片上的第二芯片，其中所述第二芯片的侧表面是化学蚀刻表面; 以及设置在所述第一芯片和所述第二芯片之间的结合体，使得所述第一芯片和所述第二芯片彼此结合。

公开(公告)号：US09293394B2

公开(公告)日：2016-03-22

申请号：US14260205

申请日：2014-04-23

Applicant: XINTEC INC.

Inventor： Bai-Yao Lou ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Tzu-Hsiang Hung

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/04 ,  H01L23/31 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/73153 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An embodiment of the invention provides a chip package which includes a substrate having a first surface and a second surface; a conducting pad structure located on the first surface; a dielectric layer located on the first surface of the substrate and the conducting pad structure, wherein the dielectric layer has an opening exposing a portion of the conducting pad structure; and a cap layer located on the dielectric layer and filled into the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和第二表面的基板; 位于所述第一表面上的导电垫结构; 位于所述基板的所述第一表面上的电介质层和所述导电焊盘结构，其中所述电介质层具有暴露所述导电焊盘结构的一部分的开口; 以及位于电介质层上并填充到开口中的盖层。

公开(公告)号：US20160039663A1

公开(公告)日：2016-02-11

申请号：US14819174

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Chien-Min LIN

IPC: B81B7/00 ,  H01L21/48 ,  B81C1/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2207/096 ,  B81C1/00301 ,  B81C1/00682 ,  B81C2203/0118 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.

Abstract translation: 一种方法包括在插入器的下表面上形成凸块。 形成第一绝缘层以覆盖下表面和凸起。 形成从插入件的下表面延伸到上表面的沟槽。 形成聚合物支持粘合剂层以围绕凸起并且在插入器和半导体芯片之间耦合。 半导体芯片具有至少一个感测部件和电连接到感测部件的导电焊盘，并且凸块连接到导电焊盘。 通孔形成为从上部向下表面延伸。 形成第二绝缘层以覆盖上表面和通孔。 在第二绝缘层和通孔中形成再分布层。 形成包装层以覆盖再分布层并具有第二开口。

公开(公告)号：US09236429B2

公开(公告)日：2016-01-12

申请号：US14699261

申请日：2015-04-29

Applicant: XINTEC INC.

Inventor： Yu-Lin Yen ,  Sheng-Hao Chiang ,  Hung-Chang Chen ,  Ho-Ku Lan ,  Chen-Mei Fan

IPC: H01L27/14 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0642 ,  H01L21/76229 ,  H01L27/1463 ,  H01L27/14683

Abstract: A semiconductor structure includes a substrate, a dam element, a first isolation layer, a second isolation layer, and a conductive layer. The substrate has a conductive pad, a trench, a sidewall, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the second surface. The trench has a first opening at the first surface, and has a second opening at the second surface. The dam element is located on the second surface and covers the second opening. The dam element has a concave portion that is at the second opening. The first isolation layer is located on a portion of the sidewall. The second isolation layer is located on the first surface and the sidewall that is not covered by the first isolation layer, such that an interface is formed between the first and second isolation layers.

Abstract translation: 半导体结构包括基板，阻挡元件，第一隔离层，第二隔离层和导电层。 衬底具有导电焊盘，沟槽，侧壁，第一表面和与第一表面相对的第二表面。 导电垫位于第二表面上。 沟槽在第一表面具有第一开口，并且在第二表面具有第二开口。 坝体元件位于第二表面并覆盖第二开口。 坝体元件具有在第二开口处的凹入部分。 第一隔离层位于侧壁的一部分上。 第二隔离层位于不被第一隔离层覆盖的第一表面和侧壁上，使得在第一和第二隔离层之间形成界面。

公开(公告)号：US20150325557A1

公开(公告)日：2015-11-12

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/17 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/146 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract translation: 提供了包括第一基板的芯片封装。 第一基板包括感测装置。 第二基板附着在第一基板上并且包括集成电路装置。 第一导电结构通过设置在第一基板上的再分配层电连接到感测装置和集成电路装置。 绝缘层覆盖第一基板，第二基板和再分布层。 绝缘层在其中具有孔，并且第二导电结构设置在孔的底部下方。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US09184092B2

公开(公告)日：2015-11-10

申请号：US14214408

申请日：2014-03-14

Applicant: XINTEC INC.

Inventor： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L21/44 ,  H01L21/768 ,  B81B7/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method for forming a chip package, by providing a substrate having a plurality of conducting pads below a lower surface, and a dielectric layer located between the conducting pads, forming a recess in an upper surface of the substrate, forming a hole extending through the bottom of the recess, forming an insulating layer on the sidewall of the recess and in the hole, exposing a portion of the conducting pads through the insulating layer, and forming a conducting layer on the insulating layer and through the hole to contact with the conducting pads.

Abstract translation: 一种用于形成芯片封装的方法，通过提供在下表面下方具有多个导电焊盘的衬底以及位于导电焊盘之间的电介质层，在衬底的上表面中形成凹陷，形成贯穿 在所述凹部的所述侧壁上形成绝缘层，并且在所述孔中形成绝缘层，使所述导电焊盘的一部分通过所述绝缘层露出，并且在所述绝缘层上形成导电层，并且穿过所述孔与所述导电体 垫

公开(公告)号：US09177919B2

公开(公告)日：2015-11-03

申请号：US14540460

申请日：2014-11-13

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/28

CPC classification number: H01L23/5386 ,  B81B7/0064 ,  B81B2207/096 ,  H01L21/561 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/29011 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48471 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package including a first substrate having a first surface and a second surface opposite thereto is provided. The first substrate has a micro-electric element and a plurality of conducting pads adjacent to the first surface. The first substrate has a plurality of openings respectively exposing a portion of each conducting pad. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conducting pads.

Abstract translation: 提供了包括具有第一表面和与其相对的第二表面的第一基板的芯片封装。 第一基板具有微电元件和与第一表面相邻的多个导电垫。 第一基板具有分别暴露每个导电垫的一部分的多个开口。 第二基板设置在第一表面上。 封装层设置在第一表面上并覆盖第二基板。 再分配层设置在第二表面上并延伸到开口中以电连接导电垫。

公开(公告)号：US09177905B2

公开(公告)日：2015-11-03

申请号：US14036954

申请日：2013-09-25

Applicant: XINTEC INC.

Inventor： Yu-Ting Huang ,  Tsang-Yu Liu

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  B81B7/00 ,  H01L23/31

CPC classification number: H01L23/49827 ,  B81B7/0061 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/481 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A chip package for a sensing element. The chip package includes a substrate having a first surface and a second surface, and a sensing layer having a sensing region disposed on the first surface of the substrate. A conducting pad structure is disposed on the substrate and electrically connected to the sensing region, and a spacer layer is disposed on the first surface of the substrate. A semiconductor substrate is place on the spacer layer. The semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region. A through-hole extends from a surface of the semiconductor substrate toward the substrate, and connects to the cavity.

Abstract translation: 用于传感元件的芯片封装。 芯片封装包括具有第一表面和第二表面的基板，以及具有设置在基板的第一表面上的感测区域的感测层。 导电焊盘结构设置在基板上并电连接到感测区域，并且间隔层设置在基板的第一表面上。 半导体衬底位于间隔层上。 半导体衬底，间隔层和衬底一起围绕感测区域上的空腔。 通孔从半导体衬底的表面朝向衬底延伸，并连接到空腔。

公开(公告)号：US20150287659A1

公开(公告)日：2015-10-08

申请号：US14676671

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L23/31 ,  H01L21/50 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L21/02

CPC classification number: H01L23/3114 ,  G01K1/00 ,  G01L19/0627 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L2021/60022 ,  H01L2224/02371 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing device and a conducting pad therein. The sensing device and the conducting pad are adjacent to the first surface. The conducting pad has a sidewall laterally protruding from a sidewall of the substrate. An encapsulation layer is attached to the first surface of the substrate to cover the sensing device and the conducting pad. A redistribution layer is disposed on the second surface of the substrate and extends to contact the sidewall of the conducting pad. An end of the redistribution layer protrudes from the first surface of the substrate and is level with a third surface of the encapsulation layer that is opposite to the first surface. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有第一表面和与其相对的第二表面的基板。 基板包括感测装置和导电垫。 感测装置和导电垫与第一表面相邻。 导电垫具有从衬底的侧壁侧向突出的侧壁。 封装层附接到基板的第一表面以覆盖感测装置和导电垫。 再分配层设置在衬底的第二表面上并延伸以接触导电焊盘的侧壁。 再分布层的一端从衬底的第一表面突出并且与封装层的与第一表面相对的第三表面平齐。 还提供了一种形成芯片封装的方法。