公开(公告)号：US07884392B2

公开(公告)日：2011-02-08

申请号：US12362210

申请日：2009-01-29

Applicant: Hyuek-Jae Lee ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

Inventor： Hyuek-Jae Lee ,  Tae-Je Cho ,  Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC: H01L31/0328

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.

Abstract translation: 本文示例性描述的一个实施例可以被表征为包括具有前表面和后表面的基板的图像传感器; 在所述基板的前表面上的光电转换部; 贯穿所述基板延伸的通孔，其中所述通孔电连接到所述光电转换部分; 在所述基板的后表面上的外部连接端子，其中所述外部连接端子连接到所述通孔; 以及形成在所述基板的后表面的一部分上的遮光层，其中所述遮光层相对于外部光基本上是不透明的。 在一些实施例中，其上形成有遮光层的基板的后表面的部分不与通孔或外部连接端子重叠。

公开(公告)号：US20100019338A1

公开(公告)日：2010-01-28

申请号：US12574906

申请日：2009-10-07

Applicant: Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

Inventor： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC: H01L25/04

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

Abstract translation: 堆叠型半导体芯片封装包括在晶片级工艺中堆叠的第一晶片模具，保护基板和第二晶片模具。 第一晶片模具包括具有第一焊盘的第一芯片和封装第一芯片的第一模具层。 保护基板被放置在第一晶片模具上，使用第一粘合剂层与第一晶片模具机械结合，并且包括面向第一焊盘的布线层。 第二晶片模具放置在第一晶片模具下面，使用第二粘合剂层与第一晶片模具机械结合，并且包括具有第二焊盘的第二芯片和封装第二芯片的第二模具层。 第一通孔将保护衬底的布线层与第二衬垫电连接。 第二通孔将保护基板的布线层与外部连接端子电连接。

公开(公告)号：US20090200632A1

公开(公告)日：2009-08-13

申请号：US12362210

申请日：2009-01-29

Applicant: Hyuek-Jae LEE ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

Inventor： Hyuek-Jae LEE ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.

Abstract translation: 本文示例性描述的一个实施例可以被表征为包括具有前表面和后表面的基板的图像传感器; 在所述基板的前表面上的光电转换部; 贯穿所述基板延伸的通孔，其中所述通孔电连接到所述光电转换部分; 在所述基板的后表面上的外部连接端子，其中所述外部连接端子连接到所述通孔; 以及形成在所述基板的后表面的一部分上的遮光层，其中所述遮光层相对于外部光基本上是不透明的。 在一些实施例中，其上形成有遮光层的基板的后表面的部分不与通孔或外部连接端子重叠。

公开(公告)号：US07554201B2

公开(公告)日：2009-06-30

申请号：US11513173

申请日：2006-08-31

Applicant: Uu-Byung Kang ,  Yong-Hwan Kwon ,  Jong-Ho Lee ,  Chung-Sun Lee

Inventor： Uu-Byung Kang ,  Yong-Hwan Kwon ,  Jong-Ho Lee ,  Chung-Sun Lee

IPC: H01L23/48

CPC classification number: C22C30/06 ,  B23K35/025 ,  B23K35/262 ,  B23K35/264 ,  B23K2101/40 ,  C22C12/00 ,  C22C13/00 ,  C22C13/02 ,  C22C30/02 ,  C22C30/04 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3463 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Example embodiments of the present invention relate to an alloy solder and a semiconductor device using the alloy solder. Other example embodiments relate to an alloy solder capable of increasing reliability of a junction between a semiconductor chip and a substrate. According to still In still other example embodiments of the present invention, there may be a tin-bismuth (Sn—Bi) family alloy solder between a semiconductor chip and a substrate, and a semiconductor device using the alloy solder. The semiconductor device may include a semiconductor chip formed with a plurality of gold bumps, a substrate having metal wirings connected to the gold bumps, and a junction including a tin-bismuth family alloy solder interposed between and connecting the gold bump and the metal wiring.

Abstract translation: 本发明的示例性实施例涉及合金焊料和使用该合金焊料的半导体器件。 其他示例实施例涉及能够增加半导体芯片和基板之间的结的可靠性的合金焊料。 根据本发明的另一个示例性实施例，可以在半导体芯片和基板之间存在锡 - 铋（Sn-Bi）族合金焊料，以及使用该合金焊料的半导体器件。 半导体器件可以包括形成有多个金凸块的半导体芯片，具有连接到金凸块的金属布线的基板以及插入在金凸块和金属布线之间并连接金凸块和金属布线的锡 - 铋系合金焊料的接合部。

公开(公告)号：US20080242000A1

公开(公告)日：2008-10-02

申请号：US12139771

申请日：2008-06-16

Applicant: Yong-hwan KWON ,  Chung-sun LEE ,  Woon-byung KANG

Inventor： Yong-hwan KWON ,  Chung-sun LEE ,  Woon-byung KANG

IPC: H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.

Abstract translation: 公开了一种晶片级芯片级封装及相关的制造方法。 晶片级芯片级封装包括半导体衬底，其包括集成电路，设置在半导体衬底上并与集成电路电连接的导电球，以及由绝缘材料形成并设置在底表面和侧表面上的保护部分 的半导体衬底。

公开(公告)号：US20080083983A1

公开(公告)日：2008-04-10

申请号：US11850184

申请日：2007-09-05

Applicant: Hyang-sun JANG ,  Yong-hwan KWON ,  Un-byoung KANG ,  Chung-sun Lee ,  Woon-seong KWON

Inventor： Hyang-sun JANG ,  Yong-hwan KWON ,  Un-byoung KANG ,  Chung-sun Lee ,  Woon-seong KWON

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

Abstract: In one aspect, a bump electrode of a semiconductor device is formed by providing a substrate including a pad electrode, forming a seed layer over the pad electrode, and forming a mask layer over the seed layer which includes an opening aligned over the pad electrode. A barrier plating layer is electroplated within the opening over the seed layer, and a bump plating layer is electroplated over the barrier plating layer. The mask layer is removed, and the seed layer is etched using the bump plating layer as a mask.

Abstract translation: 一方面，通过提供包括焊盘电极的基板，在焊盘电极上形成种子层，以及在种子层上形成掩模层，形成半导体器件的突起电极，该掩模层包括在焊盘电极上对准的开口。 在种子层的开口内电镀阻挡层，在阻挡镀层上电镀凸点镀层。 去除掩模层，并使用凸块镀层作为掩模蚀刻种子层。

公开(公告)号：US20080054456A1

公开(公告)日：2008-03-06

申请号：US11828409

申请日：2007-07-26

Applicant: Un-byoung KANG ,  Yong-hwan KWON ,  Chung-sun LEE ,  Woon-seong KWON ,  Hyung-sun JANG

Inventor： Un-byoung KANG ,  Yong-hwan KWON ,  Chung-sun LEE ,  Woon-seong KWON ,  Hyung-sun JANG

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/73203 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor package includes a semiconductor chip operatively attached to a conductive lead of a film circuit substrate by an indium-containing solder material and a silver-containing bump electrode, where the solder material is interposed between the conductive lead and the bump electrode.

Abstract translation: 半导体封装包括通过含铟焊料材料和含银凸点电极可操作地附接到膜电路基板的导电引线的半导体芯片，其中焊料材料插入在导电引线和凸块电极之间。

公开(公告)号：US20070007664A1

公开(公告)日：2007-01-11

申请号：US11428169

申请日：2006-06-30

Applicant: Chung-Sun LEE ,  Yong-Hwan KWON ,  Kyoung-Sei CHOI ,  Woon-Byung KANG

Inventor： Chung-Sun LEE ,  Yong-Hwan KWON ,  Kyoung-Sei CHOI ,  Woon-Byung KANG

IPC: H01L23/48 ,  H01L21/00 ,  H01L21/44

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/562 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a semiconductor package having a semiconductor chip, a rear surface of which is molded, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip including a wafer and a metal pad formed on a front surface of the wafer; a solder ball formed on a front surface of the wafer, and electrically connected to the metal pad; and a reinforcing member formed on a rear surface of the wafer. The reinforcing member is formed of an epoxy molding compound, and the reinforcing member protrudes at least 5 μm from side surfaces of the semiconductor chip.

Abstract translation: 提供一种半导体封装，其具有半导体芯片，其后表面被模制，以及制造半导体封装的方法。 半导体封装包括：半导体芯片，包括晶片和形成在晶片前表面上的金属焊盘; 形成在所述晶片的前表面上并且电连接到所述金属焊盘的焊球; 以及形成在晶片的后表面上的加强构件。 加强构件由环氧树脂模塑料形成，并且加强构件从半导体芯片的侧表面突出至少5微米。

公开(公告)号：US20060071303A1

公开(公告)日：2006-04-06

申请号：US11218260

申请日：2005-08-31

Applicant: Chung-Sun Lee ,  Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

Inventor： Chung-Sun Lee ,  Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Kyoung-Sei Choi

IPC: H01L23/58

CPC classification number: H01L23/13 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/189 ,  H05K3/0038 ,  H05K3/027 ,  H05K3/22 ,  H05K2201/09072 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05099

Abstract: Embodiments of the present invention are directed to a film substrate of a semiconductor package. The film substrate of the semiconductor package comprises a thin film insulating substrate and a thin copper circuit pattern. An inter-pattern groove between the thin copper circuit patterns is formed by laser etching. Accordingly, the embodiment improves electrical contact between the film substrate and a semiconductor chip mounted thereon, and improves the manufacturing process for the film substrate by adopting a simple laser machining to form the thin copper circuit pattern in lieu of a traditional wet-etching process that undergoes complex lithography steps.

Abstract translation: 本发明的实施例涉及一种半导体封装的薄膜基片。 半导体封装的薄膜基板包括薄膜绝缘基板和薄铜电路图案。 通过激光蚀刻形成薄铜电路图案之间的图案间凹槽。 因此，本实施方式改善了薄膜基板与安装在其上的半导体芯片之间的电接触，并且通过采用简单的激光加工来形成薄铜电路图案来代替薄的基板的制造工艺来代替传统的湿式蚀刻工艺， 经历复杂的光刻步骤。

公开(公告)号：US20060003568A1

公开(公告)日：2006-01-05

申请号：US11086614

申请日：2005-03-21

Applicant: Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

Inventor： Kyoung-Sei Choi ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Chung-Sun Lee

IPC: H01L21/44

CPC classification number: H05K3/28 ,  H05K1/036 ,  H05K1/0393 ,  H05K3/101 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0129 ,  H05K2201/0162 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/0759 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/4916

Abstract: A method for manufacturing a tape wiring board in accordance with the present invention may employ an imprinting process in forming a wiring pattern, thereby reducing the number of processes for manufacturing a tape wiring board and allowing the manufacturing process to proceed in a single production line. Therefore, the manufacturing time and cost may be reduced. A profile of the wiring pattern may be determined by the shape of an impression pattern of a mold. This may establish the top width of inner and outer leads and incorporate fine pad pitch. Although ILB and OLB process may use an NCP, connection reliability may be established due to the soft and elastic wiring pattern.

Abstract translation: 根据本发明的制造带布线板的方法可以在形成布线图案中采用压印工艺，从而减少了用于制造带布线板的工艺的数量，并允许制造工艺在单个生产线中进行。 因此，制造时间和成本可能降低。 布线图案的轮廓可以通过模具的印模图案的形状来确定。 这可以建立内部和外部引线的顶部宽度并且结合细小的垫间距。 虽然ILB和OLB过程可能使用NCP，但是由于软和弹性布线图案可能建立连接可靠性。