公开(公告)号：US08447494B2

公开(公告)日：2013-05-21

申请号：US12361109

申请日：2009-01-28

Applicant: Zhong Wang ,  Brian Spohn ,  Miles K. Maxey ,  Jonathan J Stec ,  Timothy E. McCarthy ,  Vincent A. White ,  John F. Van Gilder ,  Lan Wang ,  Jun Lu

Inventor： Zhong Wang ,  Brian Spohn ,  Miles K. Maxey ,  Jonathan J Stec ,  Timothy E. McCarthy ,  Vincent A. White ,  John F. Van Gilder ,  Lan Wang ,  Jun Lu

IPC: G06F17/00 ,  F02M63/02 ,  F02M33/02 ,  F02M37/00

CPC classification number: B60W20/15 ,  B60L2240/441 ,  B60W10/06 ,  B60W20/00 ,  B60W2510/0638 ,  B60W2550/12 ,  B60W2710/0605 ,  B60W2710/065 ,  F02D41/00 ,  F02D41/0032 ,  F02D41/042 ,  F02D41/123 ,  F02M25/0836 ,  F02M25/089 ,  Y02T10/48 ,  Y02T10/6269 ,  Y02T90/14

Abstract: A control module for an engine of a vehicle includes a mode determination module that determines whether the vehicle is in a fuel-saving mode based on an acceleration of the vehicle. A diurnal control valve (DCV) control module selectively closes a DCV a predetermined time after at least one of determining that the vehicle is in the fuel-saving mode and determining that the engine is stopped.

Abstract translation: 用于车辆的发动机的控制模块包括模式确定模块，其基于车辆的加速度来确定车辆是否处于节油模式。 昼夜控制阀（DCV）控制模块在确定车辆处于燃料节省模式中并确定发动机停止的至少一个之后，在预定时间内选择性地关闭DCV。

公开(公告)号：US20130121551A1

公开(公告)日：2013-05-16

申请号：US13294038

申请日：2011-11-10

Applicant: Per Rugaard Poulsen ,  Walther Fledelius ,  Paul Keall ,  Elisabeth Weiss ,  Jun Lu ,  Emily Brackbill ,  Geoffrey Hugo

Inventor： Per Rugaard Poulsen ,  Walther Fledelius ,  Paul Keall ,  Elisabeth Weiss ,  Jun Lu ,  Emily Brackbill ,  Geoffrey Hugo

IPC: G06K9/00

CPC classification number: G06T11/008 ,  A61N5/1049 ,  A61N2005/1061 ,  G06T17/00 ,  G06T2210/41

Abstract: A method of determining a model of a marker includes obtaining projection images, each of the projection images having an image of a marker that indicates a shape of the marker, determining binary images of the marker for respective ones of the projection images, and constructing a three-dimensional model of the marker using the binary images, the three-dimensional model comprising a set of voxels in a three-dimensional space that collectively indicates a three-dimensional shape of the marker, wherein the act of constructing the three-dimensional model is performed using a processing unit.

Abstract translation: 确定标记的模型的方法包括获得投影图像，每个投影图像具有指示标记的形状的标记的图像，确定各个投影图像的标记的二值图像，并且构建一个 使用二值图像的标记的三维模型，三维模型包括三维空间中的一组体素，其共同表示标记的三维形状，其中构建三维模型的动作 使用处理单元执行。

公开(公告)号：US20130049100A1

公开(公告)日：2013-02-28

申请号：US13216122

申请日：2011-08-23

Applicant: Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

Inventor： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/8309 ,  H01L2224/83141 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

Abstract translation: 本发明涉及功率半导体器件及其制备方法。 特别地，本发明旨在提供一种降低功率MOSFET的Rdson（漏源电阻）的基板贡献的方法以及通过该方法制造的功率MOSFET器件。 通过在Si衬底的底部形成一个或多个底部沟槽，有效地降低归因于衬底的功率MOSFET器件的导通电阻。 与具有底槽的衬底互补的匹配引线框架底座进一步改善了功率MOSFET器件的封装。

公开(公告)号：US20120248593A1

公开(公告)日：2012-10-04

申请号：US13494219

申请日：2012-06-12

Applicant: Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

Inventor： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract translation: 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US20120235289A1

公开(公告)日：2012-09-20

申请号：US13480391

申请日：2012-05-24

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L24/73 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16245 ,  H01L2224/2784 ,  H01L2224/291 ,  H01L2224/3015 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/92 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract translation: 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US20120193695A1

公开(公告)日：2012-08-02

申请号：US13442757

申请日：2012-04-09

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L27/06

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

Abstract translation: 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US08178954B2

公开(公告)日：2012-05-15

申请号：US12693446

申请日：2010-01-26

Applicant: Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

Inventor： Yan Xun Xue ,  Anup Bhalla ,  Jun Lu

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/02

CPC classification number: H01L23/49575 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/39 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/84

Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.

Abstract translation: 用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。 半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。 半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

公开(公告)号：US08089244B2

公开(公告)日：2012-01-03

申请号：US12481689

申请日：2009-06-10

Applicant: Wei-Ming Zhang ,  Jun Lu ,  Jin Li

Inventor： Wei-Ming Zhang ,  Jun Lu ,  Jin Li

IPC: H02J7/00 ,  H02J7/02 ,  H01R13/44

CPC classification number: H01R24/68 ,  H01R2103/00

Abstract: An electronic device includes a main body, at least two pins folded mounted to the main body, and at least two conductive assemblies received in the main body. Each of the conductive assemblies includes a locking member and a resilient member resisting the locking member, when the pins are pushed and substantially perpendicular to main body, each locking member is capable of locking with an end of one of the pins.

Abstract translation: 电子设备包括主体，至少两个折叠安装到主体的销以及容纳在主体中的至少两个导电组件。 每个导电组件包括锁定构件和抵抗锁定构件的弹性构件，当销被推动并且基本上垂直于主体时，每个锁定构件能够与其中一个销的端部锁定。

公开(公告)号：US08076183B2

公开(公告)日：2011-12-13

申请号：US12606290

申请日：2009-10-27

Applicant: Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

Inventor： Yan Xun Xue ,  Jun Lu ,  Le Shi ,  Liang Zhao

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L24/73 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/29339 ,  H01L2224/371 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/83101 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

Abstract translation: 公开了一种将引线框封装内的互连板连接到半导体管芯的方法。 基座引线框架设置有用于附接半导体管芯的管芯焊盘。 提供互连板，用于附接到基底引线框架和半导体管芯。 将基准注册功能添加到基准引线框架和板对准特征到互连板上，其中配准特征被设计成彼此匹配，使得在互连板到基底引线框架的接近时，两个配准特征将相互接合并引导彼此引起伴随 互连板与基座引线框架的自对准连接。 接下来，使互连板靠近基底引线框架以将板对准特征接合并锁定到基准对准特征，从而完成互连板连接到半导体管芯并形成引线框封装。

公开(公告)号：US20110262517A1

公开(公告)日：2011-10-27

申请号：US12594777

申请日：2008-04-07

Applicant: Jun O. Liu ,  Curtis R. Chong ,  Jing Xu ,  Jun Lu ,  Shridhar Bhat

Inventor： Jun O. Liu ,  Curtis R. Chong ,  Jing Xu ,  Jun Lu ,  Shridhar Bhat

IPC: A61K9/00 ,  A61K31/496 ,  A61P35/00 ,  A61K39/395 ,  A61P27/02 ,  C12Q1/26 ,  A61K31/4178

CPC classification number: A61K31/415 ,  A61K9/0019 ,  A61K9/0024 ,  A61K31/497 ,  C12Q1/25 ,  G01N2500/00 ,  Y02A50/401

Abstract: Described herein are methods of inhibiting angiogenesis, and treating or preventing a disease or disorder (or symptoms thereof) associated with angiogenesis, wherein an anti-angiogenesis compound is administered to a subject.

Abstract translation: 本文描述了抑制血管发生，治疗或预防与血管发生相关的疾病或病症（或其症状）的方法，其中向受试者施用抗血管生成化合物。