公开(公告)号：US09179320B2

公开(公告)日：2015-11-03

申请号：US12907581

申请日：2010-10-19

Applicant: Won Jae Shin ,  Young Jun Hong ,  Chang Yong Shin ,  Yong Ho Cho ,  Dong Jo Park ,  Jung Hyun Park

Inventor： Won Jae Shin ,  Young Jun Hong ,  Chang Yong Shin ,  Yong Ho Cho ,  Dong Jo Park ,  Jung Hyun Park

IPC: H04W16/02 ,  H04L5/00 ,  H04W16/32 ,  H04W84/04

CPC classification number: H04W36/0083 ,  H04L5/0048 ,  H04W16/02 ,  H04W16/32 ,  H04W36/30 ,  H04W84/045

Abstract: A method of assigning and managing reference signals in a multi-cell environment, and a network device and a terminal for applying the method, are provided. Reference signal patterns may be assigned to multiple femtocells through a long term coordination of a central control unit that is used to control multiple cells.

Abstract translation: 提供了一种在多小区环境中分配和管理参考信号的方法，以及用于应用该方法的网络设备和终端。 可以通过用于控制多个小区的中央控制单元的长期协调来将参考信号模式分配给多个毫微微小区。

公开(公告)号：US08986555B2

公开(公告)日：2015-03-24

申请号：US12892047

申请日：2010-09-28

Applicant: Ji-Eun Kim ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

Inventor： Ji-Eun Kim ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

IPC: H01B13/00 ,  H05K3/40 ,  H05K3/06 ,  H05K3/20

CPC classification number: H05K3/4007 ,  H05K3/061 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2203/0152 ,  H05K2203/0376

Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.

Abstract translation: 公开了一种制造具有凸块的印刷电路板的方法。 该方法包括制备其上形成有第一电路的第一载体，将第一载体压缩到绝缘层的一个表面，使得第一电路被掩埋，根据凸点将在第一载体上堆叠抗蚀剂 通过蚀刻第一载体形成和形成凸块。 根据本发明的实施例，可以减小印刷电路板中的凸块与其相邻凸块之间的高度差，从而可以更好地实现电子部件和印刷电路板之间的电连接。

公开(公告)号：US08633392B2

公开(公告)日：2014-01-21

申请号：US13354438

申请日：2012-01-20

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

Abstract translation: 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

公开(公告)号：US08546943B2

公开(公告)日：2013-10-01

申请号：US12923037

申请日：2010-08-30

Applicant: Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L23/13 ,  H01L23/498

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract translation: 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。

公开(公告)号：US08515357B2

公开(公告)日：2013-08-20

申请号：US12349303

申请日：2009-01-06

Applicant: Hyun Ho Choi ,  Yong Ho Cho ,  Jung Hyun Park ,  Dong Jo Park

Inventor： Hyun Ho Choi ,  Yong Ho Cho ,  Jung Hyun Park ,  Dong Jo Park

IPC: H04B17/00 ,  H04B15/00

CPC classification number: H04L27/2649 ,  H04W16/14 ,  H04W72/02

Abstract: A cognitive radio (CR) communication apparatus and method is provided. A cognitive radio (CR) communication apparatus includes a signal receiving unit which receives signals from a primary user of a primary system and a secondary transmitter of a secondary system, the received signals including an element associated with at least one known signal of the secondary transmitter, and a determination unit which determines whether a signal of the primary user exists from among the received signals based on the element associated with the at least one known signal.

公开(公告)号：US08420878B2

公开(公告)日：2013-04-16

申请号：US12577869

申请日：2009-10-13

Applicant: Chae-Ho Shin ,  Jung-Hyun Park ,  Eunae Noh ,  Kyoungho Row ,  Ji Won Park

Inventor： Chae-Ho Shin ,  Jung-Hyun Park ,  Eunae Noh ,  Kyoungho Row ,  Ji Won Park

IPC: C07C5/333 ,  B01J23/18

CPC classification number: B01J23/8876 ,  B01J23/002 ,  B01J35/0006 ,  B01J35/1009 ,  B01J35/1038 ,  B01J37/03 ,  B01J37/10 ,  B01J2523/00 ,  C07C5/48 ,  C07C2523/18 ,  C07C2523/28 ,  C07C2523/745 ,  C07C11/167 ,  B01J2523/54 ,  B01J2523/68 ,  B01J2523/842

Abstract: The present invention relates to a complex oxide catalyst of Bi/Mo/Fe and an oxidative dehydrogenation of 1-butene in the presence of a catalyst herein. A catalyst of the present invention is superior to the conventional Bi/Mo catalyst in thermal and mechanical stabilities, conversion and selectivity toward 1,3-butadiene, while showing a long-term catalytic activity.

Abstract translation: 本发明涉及Bi / Mo / Fe的复合氧化物催化剂和1-丁烯在本文催化剂存在下的氧化脱氢。 本发明的催化剂在热和机械稳定性，转化率和对1,3-丁二烯的选择性方面优于传统的Bi / Mo催化剂，同时显示出长期的催化活性。

公开(公告)号：US20130037004A1

公开(公告)日：2013-02-14

申请号：US13642276

申请日：2010-10-26

Applicant: Deuk-Jin Park ,  Eung-Sung Kim ,  Ju-Tae Kim ,  Kang-Yun Jung ,  Kwang-Cheol Heo ,  Jong-Suk Kim ,  Jung-Hyun Park ,  Eun Ha ,  Beom-Yong No

Inventor： Deuk-Jin Park ,  Eung-Sung Kim ,  Ju-Tae Kim ,  Kang-Yun Jung ,  Kwang-Cheol Heo ,  Jong-Suk Kim ,  Jung-Hyun Park ,  Eun Ha ,  Beom-Yong No

IPC: F02M69/04

CPC classification number: F02M45/086 ,  F02M47/027 ,  F02M61/182 ,  F02M2200/46

Abstract: The present invention provides a two solenoid valve relay with a two-phase fuel injection valve for a diesel engine, which is installed on a valve itself to enable injection at pressure greater than opening pressure, at which the fuel enters into a fuel valve, thereby improving fuel injection performance, and which is configured to enable adjustment of an injection timing at the opening pressure within the valve, wherein injection timings through a solenoid valve is provided for low load and high load, respectively, such that a distinct difference exists between the injection timings to open the nozzle hole of the nozzle in a differential manner at pressure higher than the pressure, at which the fuel enters to the fuel valve and internal spring opening pressure, thereby injecting fuel at high pressure even at low load to facilitate vaporization, and wherein, in case of a high speed operation or high load, low pressure/high pressure needle valves are opened at the same time to quickly inject fuel of a high volume through a plurality of nozzle holes, thereby improving combustion performance of an engine, and wherein a space between the needle valve and the nozzle hole which are closed after the injection is minimized because the nozzle hole is opened differentially and sequentially according to pressure, thereby avoiding waste of fuel and reducing harmful gas (smoke, Nox).

Abstract translation: 本发明提供了一种具有用于柴油发动机的两相燃料喷射阀的两个电磁阀继电器，该电磁阀继电器安装在阀本身上以能够在大于开启压力的压力下喷射燃料进入燃料阀，由此 提高燃料喷射性能，并且其被配置为能够调节阀内的打开压力下的喷射正时，其中通过电磁阀分别为低负载和高负载提供喷射定时，使得在 喷射正时以不同于燃料进入燃料阀的压力和内部弹簧开启压力的压力以不同的方式打开喷嘴的喷嘴孔，从而甚至在低负载下高压喷射燃料以促进汽化， 并且其中，在高速运转或高负载的情况下，低压/高压针阀同时打开以快速地 通过多个喷嘴孔大体积的喷射燃料，从而改善发动机的燃烧性能，并且其中在喷射之后关闭的针阀和喷嘴孔之间的空间被最小化，因为喷嘴孔差异地并且顺序地打开 根据压力，从而避免燃料的浪费和减少有害气体（烟雾，Nox）。

公开(公告)号：US20120015490A1

公开(公告)日：2012-01-19

申请号：US13183630

申请日：2011-07-15

Applicant: Kwan-Heum LEE ,  Soon-Wook JUNG ,  Jung-Hyun PARK ,  Wook-Je KIM ,  Jong-Sang BAN

Inventor： Kwan-Heum LEE ,  Soon-Wook JUNG ,  Jung-Hyun PARK ,  Wook-Je KIM ,  Jong-Sang BAN

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅极结构; 形成牺牲隔离物可以形成在栅极衬底的侧壁上; 通过使用栅极结构和牺牲隔离物作为离子注入掩模的第一离子注入工艺将第一杂质注入到衬底的部分中以形成源区和漏区; 去除牺牲隔离物; 以及通过使用所述栅极结构作为离子注入掩模的第二离子注入工艺将第二杂质和碳原子注入到所述衬底的部分中，以分别形成源极和漏极延伸区域和碳掺杂区域。

公开(公告)号：US20110259627A1

公开(公告)日：2011-10-27

申请号：US13067883

申请日：2011-07-01

Applicant: Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Ji-Eun Kim ,  Jeong-Woo Park ,  Jung-Hyun Park

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K3/205 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0435 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator.

Abstract translation: 电路板包括：具有凹槽的绝缘体; 填充所述凹槽的一部分的电路层; 电路层上的填充凹槽其余部分的焊盘; 以及与电路层电连接的电路图案，电路图案埋在绝缘体中，使得电路图案的一部分在绝缘体的表面露出。

公开(公告)号：US20110110058A1

公开(公告)日：2011-05-12

申请号：US12748082

申请日：2010-03-26

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

IPC: H05K7/02 ,  H05K3/00

CPC classification number: H05K3/00 ,  H01L2224/16225 ,  H05K3/30 ,  Y10T29/49124

Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component.

Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，片上封装衬底上的单层板包括形成在绝缘体上表面上的绝缘体，电路图案和倒装焊接焊盘，导体凸块， 与电路图案的下表面接触并穿透绝缘体，阻焊层，其形成在绝缘体的上表面上，使得至少一部分倒装芯片接合焊盘露出，并且 倒装芯片焊接凸块，其形成在倒装焊盘的上表面上，以便与电子部件进行倒装芯片连接。