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    Fabrication method of semiconductor package structure
    22.
    发明授权
    Fabrication method of semiconductor package structure 有权
    半导体封装结构的制造方法

    公开(公告)号：US08304268B2

    公开(公告)日：2012-11-06

    申请号：US12770059

    申请日：2010-04-29

    申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L21/44

    CPC分类号： H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

    摘要翻译： 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

    Package structure having MEMS element and fabrication method thereof
    23.
    发明授权
    Package structure having MEMS element and fabrication method thereof 有权
    具有MEMS元件的封装结构及其制造方法

    公开(公告)号：US08154115B1

    公开(公告)日：2012-04-10

    申请号：US13024672

    申请日：2011-02-10

    申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Shih-Kuang Chiu

    发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Shih-Kuang Chiu

    IPC分类号： H01L23/12

    CPC分类号： B81B7/007 ,  B81C2203/0154 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A package structure having an MEMS element includes: a chip having at least an MEMS element and a plurality of first conductive pads; a lid disposed on the chip to cover the MEMS element and having a plurality of second conductive pads formed thereon; a plurality of bonding wires electrically connecting the first and second conductive pads; a plurality of first bumps disposed on the second conductive pads, respectively; an encapsulant formed on the chip to encapsulate the lid, the bonding wires, the first and second conductive pads and the first bumps while exposing the top surfaces of the first bumps; and a plurality of circuits formed on the encapsulant and electrically connecting to the exposed first bumps, thereby avoiding the conventional drawback of electrical connection failure caused by position deviation of bonding wires due to mold flow of the encapsulant.

    摘要翻译： 具有MEMS元件的封装结构包括：具有至少MEMS元件和多个第一导电焊盘的芯片; 设置在所述芯片上以覆盖所述MEMS元件并且具有形成在其上的多个第二导电焊盘的盖; 电连接第一和第二导电焊盘的多个接合线; 分别设置在第二导电焊盘上的多个第一凸块; 密封剂，形成在所述芯片上以封装所述盖，所述接合线，所述第一和第二导电焊盘和所述第一凸起，同时暴露所述第一凸块的顶表面; 以及形成在密封剂上并与露出的第一凸起电连接的多个电路，从而避免了由于密封剂的模具流动导致的接合线的位置偏移导致的电连接故障的常规缺点。

    CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF
    24.
    发明申请
    CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
    芯片尺寸包装及其制造方法

    公开(公告)号：US20120013006A1

    公开(公告)日：2012-01-19

    申请号：US12955613

    申请日：2010-11-29

    申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L23/485 ,  H01L21/786

    CPC分类号： H01L21/561 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/96 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/96 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2924/00

    摘要： A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost.

    摘要翻译： 提供了一种芯片级封装的制造方法，其包括在芯片的有源表面上形成保护层并将芯片的非活性表面固定到透明载体上; 进行成型工序; 从芯片上除去保护层并执行再分配层（RDL）工艺，从而解决了将芯片直接附着在粘合膜上所引起的常规问题，例如由热引起的膜软化，密封剂溢出，翘曲，芯片偏差和 污染导致在RDL工艺中形成的布线层与芯片电极焊盘之间的电连接不良，甚至结果导致废品。 此外，本发明中使用的透明载体可以通过激光分离并在该过程中重复使用以帮助降低制造成本。

    Method for making a semiconductor package
    26.
    发明授权
    Method for making a semiconductor package 有权
    制造半导体封装的方法

    公开(公告)号：US06309914B1

    公开(公告)日：2001-10-30

    申请号：US09285629

    申请日：1999-04-03

    申请人： Chien-Ping Huang ,  Chun-Chi Ke

    发明人： Chien-Ping Huang ,  Chun-Chi Ke

    IPC分类号： H01L2144

    CPC分类号： H01L21/565 ,  H01L24/45 ,  H01L24/97 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A method for making a semiconductor package is provided for removing from the semiconductor package excess encapsulant formed by molding compound solidified in the runners and gates of a mold after transfer molding is completed without damaging the semiconductor package. A separator is used to be mounted on a BGA substrate of the semiconductor package for the excess encapsulant to attach thereon, so that the substrate requires no cleaning treatment after transfer molding is completed. In the method, the semiconductor chip is firstly adhered to and electrically connects with the substrate. The substrate with the semiconductor chip is then mounted with the separator having at least one opening for receiving the semiconductor chip, thereby the runners and gates of the mold are positioned over the separator instead of the substrate during transfer molding, allowing the excess encapsulant to attach to the separator. The presence of the separator thus eliminates damages to the substrate caused by the removal of excess encapsulant from the separator and reduces the manufacturing cost of the semiconductor chip for that the separator is capable of repetitive use.

    摘要翻译： 提供一种制造半导体封装的方法，用于从半导体封装中去除在传输模制完成之后，通过模塑固化在模具中的浇口和模具中的复合材料形成的多余的密封剂，而不损坏半导体封装。 分离器被用于安装在半导体封装的BGA衬底上，用于使多余的密封剂附着在其上，使得在传送模制完成之后，衬底不需要清洁处理。 在该方法中，首先将半导体芯片粘附并与基板电连接。 然后，具有半导体芯片的基板安装有具有至少一个用于接收半导体芯片的开口的隔板，由此在传送模塑期间模具的浇道和浇口位于隔板上而不是基板上，允许多余的密封剂附着 到分离器。 因此，分离器的存在消除了由分离器去除多余的密封剂而导致的对基板的损坏，并降低了半导体芯片的制造成本，因为隔板能够重复使用。