公开(公告)号：US09349658B1

公开(公告)日：2016-05-24

申请号：US14608625

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Bruce Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Kern Rim

IPC: H01L29/66 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/845 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of insulating material in the trenches so as to cover a portion, but not all, of the sidewalls of the lower portion of the fin, forming a second layer of insulating material above the first oxidation-blocking layer of insulating material, and performing a thermal anneal process to convert part, but not all, of the lower portion of the fin positioned above the first oxidation-blocking layer of insulating material into an oxide fin isolation region positioned under the fin.

Abstract translation: 一个说明性实施例涉及在衬底中形成多个沟槽以限定翅片，在沟槽中形成绝缘材料的第一氧化阻挡层，以便覆盖下部分的侧壁的一部分但不是全部 在绝缘材料的第一氧化阻挡层之上形成第二绝缘材料层，并进行热退火处理以将位于第一氧化阻挡层之上的翅片的下部的部分转化而不是全部 绝缘材料层形成位于翅片下方的氧化物鳍片隔离区域。

公开(公告)号：US09337259B2

公开(公告)日：2016-05-10

申请号：US14154438

申请日：2014-01-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz ,  Balasubramanian Pranatharthiharan

IPC: H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

Abstract: A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

Abstract translation: 改进ETSOI MOSFET器件的结构包括具有至少覆盖在第二半导体层上的氧化物层上的第一半导体层的区域的晶片。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔没有完全着陆，至少部分地延伸到STI中，并且绝缘材料沉积在孔中。

公开(公告)号：US09330908B2

公开(公告)日：2016-05-03

申请号：US13925911

申请日：2013-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L21/8258 ,  H01L21/8238 ,  H01L27/088

CPC classification number: H01L21/02538 ,  H01L21/02373 ,  H01L21/02441 ,  H01L21/02447 ,  H01L21/02494 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/088

Abstract: A semiconductor structure includes a first semiconductor region. The first semiconductor region includes a first semiconductor layer composed of a group IV semiconductor material having a top surface and a back surface. The first semiconductor layer has an opening in the top surface to at least a depth greater than an aspect ratio trapping (ART) distance. The first semiconductor region also has a second semiconductor layer composed of a group III/V semiconductor compound deposited within the opening and on the top surface of the first semiconductor layer. The second semiconductor layer forms an ART region from the bottom of the opening to the ART distance.

Abstract translation: 半导体结构包括第一半导体区域。 第一半导体区域包括由具有顶表面和后表面的IV族半导体材料组成的第一半导体层。 第一半导体层在顶表面具有至少大于纵横比捕获（ART）距离的深度的开口。 第一半导体区域还具有由沉积在第一半导体层的开口内和顶表面上的III / V族半导体化合物构成的第二半导体层。 第二半导体层从开口的底部到ART距离形成ART区域。

公开(公告)号：US09324797B2

公开(公告)日：2016-04-26

申请号：US14751761

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

Abstract: A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US09281198B2

公开(公告)日：2016-03-08

申请号：US13900808

申请日：2013-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

IPC: H01L21/28 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78648 ,  H01L21/28008 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42364

Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.

Abstract translation: 公开了一种形成半导体器件的方法。 该方法包括在基底上形成第一介电层; 在所述第一电介质层上形成一组偏置线; 用第二电介质层覆盖该组偏置线; 在所述第二电介质层上形成半导体层; 以及在所述偏置线组之上的半导体层上形成一组器件。

公开(公告)号：US09269629B2

公开(公告)日：2016-02-23

申请号：US14528830

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/26506 ,  H01L21/26566 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/78

Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).

公开(公告)号：US09240497B2

公开(公告)日：2016-01-19

申请号：US14167499

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kerber

IPC: H01L21/338 ,  H01L29/812 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808

CPC classification number: H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

Abstract: A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

公开(公告)号：US09236480B2

公开(公告)日：2016-01-12

申请号：US14044120

申请日：2013-10-02

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

Abstract translation: 所公开的一种方法包括在第一和第二散热片之间形成凸起的隔离柱结构，其中所述凸起的隔离柱结构分别部分地限定所述第一和第二鳍之间的第一和第二空间，并且形成围绕所述第一和第二鳍的栅极结构 和第二鳍片和凸起的隔离柱结构，其中栅极结构的至少一部分位于第一和第二空间中。 一个说明性装置尤其包括第一和第二散热片，位于第一和第二散热片之间的凸起的隔离柱结构，由翅片和凸起的隔离柱结构限定的第一和第二空间以及围绕一部分 的翅片和隔离柱结构。

公开(公告)号：US09224607B2

公开(公告)日：2015-12-29

申请号：US14029896

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

IPC: H01L27/146 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/28 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/66628

Abstract: A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region.

Abstract translation: 半导体器件包括具有相反极性的第一器件区域和第二器件区域。 每个器件区域至少包括晶体管器件和相关联的外延。 形成高k屏障以仅覆盖第一器件区域外延。 高k屏障可以包括形成在第一器件区域外延的顶表面上的基本上水平的部分和形成在第一器件区域外延的外表面上的基本上垂直的部分。 基本上垂直的部分可以将第一器件区域与第二器件区域部分隔离。

公开(公告)号：US09219114B2

公开(公告)日：2015-12-22

申请号：US13940280

申请日：2013-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Eric C. Harley ,  Terence B. Hook ,  Ali Khakifirooz ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76264 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.

Abstract translation: 形成由半导体层的顶表面悬挂并由栅极结构支撑的半导体鳍片。 在半导体层的顶表面和栅极结构之间形成绝缘体层。 形成栅极间隔物，通过各向异性蚀刻去除半导体鳍片的物理暴露部分。 随后，可以用锥形蚀刻绝缘体层的物理暴露部分。 或者，可以在绝缘体层的各向异性蚀刻之前形成一次性间隔件。 跨过栅极结构的电介质层中的两个开口之间的横向距离大于栅极间隔物的外侧壁之间的横向距离。 可以进行半导体材料的选择性沉积以形成凸起的活性区域。