公开(公告)号：US20130234315A1

公开(公告)日：2013-09-12

申请号：US13414877

申请日：2012-03-08

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

摘要： Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

摘要翻译： 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

公开(公告)号：US08513814B2

公开(公告)日：2013-08-20

申请号：US13098816

申请日：2011-05-02

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02126 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05664 ,  H01L2224/061 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/141 ,  H01L2224/14104 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.

摘要翻译： 结构提供有用于焊料凸块的凸起缓冲垫。 还提供了用于形成用于焊料凸块的凸起缓冲垫的方法。 该方法包括在焊料凸块连接的最后金属层的拉伸侧上形成升高的局部缓冲垫结构。 凸起的局部缓冲垫结构相对于最后一个金属层的压缩侧增加焊料凸块连接的焊盘结构的一部分的高度。

公开(公告)号：US08373275B2

公开(公告)日：2013-02-12

申请号：US12021321

申请日：2008-01-29

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/485

CPC分类号： H01L24/11 ,  H01L2224/02125 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05552

摘要： A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing.

摘要翻译： 具有用于电子封装中的内置应力缓冲器的细间距焊料凸块结构以及具有内置应力缓冲器的细间距焊料凸块结构的制造方法。 采用非常厚的最终钝化层，其由作为UBM（BLM）焊盘和焊料材料的最小厚度的所谓的缓冲层的聚酰亚胺构成，同时完全分离得到的聚酰亚胺岛，使得聚酰亚胺材料提供 大部分物理高度用于修改C4（可控崩溃芯片连接）结构的对立。 在采用聚酰亚胺材料作为垂直芯片封装互连的主要结构部件时，通过有效降低芯片制造加工步骤中遇到的高应力，可以充分利用聚酰亚胺材料的固有应力缓冲性能， 作为芯片连接，回流，预处理和可靠性热循环应力。

公开(公告)号：US08299568B2

公开(公告)日：2012-10-30

申请号：US13028332

申请日：2011-02-16

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/58

CPC分类号： H01L23/5258 ,  H01L23/5254 ,  H01L23/5256 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。

公开(公告)号：US08198133B2

公开(公告)日：2012-06-12

申请号：US12458441

申请日：2009-07-13

申请人： Timothy H. Daubenspeck ,  Paul Fortier ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Paul Fortier ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  David L. Questad ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/03005 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05016 ,  H01L2224/05019 ,  H01L2224/05027 ,  H01L2224/05552 ,  H01L2224/05563 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer.

摘要翻译： 控制崩溃芯片连接（C4）结构和制造方法，更具体地说是提高无铅C4互连可靠性的结构和方法。 一种结构包括球限制金属化（BLM）层和形成在BLM层上的受控崩溃芯片连接（C4）焊球。 此外，该结构包括在BLM层下面的最终金属垫层和在最终金属垫层下面的盖层。 此外，该结构包括在最终金属焊盘层和BLM层和盖层之一内的C4焊球之下形成的气隙。

公开(公告)号：US20120139113A1

公开(公告)日：2012-06-07

申请号：US12959697

申请日：2010-12-03

申请人： Charles L. Arvin ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Charles L. Arvin ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/48 ,  H01L21/3205

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0361 ,  H01L2224/0382 ,  H01L2224/03912 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.

摘要翻译： 制造半导体结构的方法包括图案化在焊料材料下形成底切的阻挡层冶金（BLM），以及在底切和焊料材料上形成修复材料。 该方法还包括从焊料材料中去除修复材料，以及回流焊料。

公开(公告)号：US08138099B1

公开(公告)日：2012-03-20

申请号：US12948079

申请日：2010-11-17

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L21/302

CPC分类号： B81C1/00325 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/06051 ,  H01L2224/11001 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/141 ,  H01L2224/14131 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81002 ,  H01L2224/81143 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

摘要： Disclosed herein is a solder self-assembly structure, an IC chip including a solder self-assembly structure, and a method of making the same. The structure includes a release layer disposed on a portion of an upper surface of the substrate, laterally spaced from a via in the substrate. A barrier layer metallization (BLM) is disposed in a first part over a portion of the substrate including a via, and in a second part over the release layer, leaving a surface of the substrate exposed between the first portion and the second portion of the BLM. A solder structure is disposed over the first and second portions of the BLM and the exposed surface of the substrate disposed there between. When the solder structure is reflowed and annealed, surface tension in the solder causes self-assembly of a three-dimensional, compliant solder structure.

摘要翻译： 这里公开了焊料自组装结构，包括焊料自组装结构的IC芯片及其制造方法。 该结构包括设置在基板的上表面的一部分上的释放层，与衬底中的通孔横向间隔开。 阻挡层金属化（BLM）被布置在包括通孔的衬底的一部分上的第一部分中，并且在释放层上的第二部分中，留下衬底的表面暴露在第一部分和第二部分之间 BLM。 焊料结构设置在BLM的第一和第二部分上以及设置在其间的衬底的暴露表面。 当焊料结构回流和退火时，焊料中的表面张力引起三维，柔性焊料结构的自组装。

公开(公告)号：US07958477B2

公开(公告)日：2011-06-07

申请号：US12046608

申请日：2008-03-12

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Jeffrey S. Zimmerman

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.

摘要翻译： 提供了故障分析工具，使用该工具的方法和设计用于设计用于保护封装期间半导体芯片中的接线故障的关键区域的掩模的设计结构。 故障分析工具包括计算机基础设施，其可操作以通过确定从芯片的中心到焊料凸块处理的位置的距离来确定在焊料凸块形成期间的布线层故障的风险区域，并且识别位置边缘处的区域 用于从芯片的中心预定距离和更大的焊料凸块工艺。

公开(公告)号：US20110012249A1

公开(公告)日：2011-01-20

申请号：US12503870

申请日：2009-07-16

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An IC chip package, in one embodiment, may include an IC chip including an upper surface including an overhang extending beyond a sidewall of the IC chip, and underfill material about the sidewall and under the overhang. The overhang prevents underfill material from extending over an upper surface of the IC chip. In another embodiment, a ball grid array (BGA) is first mounted to landing pads on a lower of two joined IC chip packages. Since the BGA is formed on the lower IC chip package first, the BGA acts as a dam for the underfill material thereon. The underfill material extends about the respective IC chip and surrounds a bottom portion of a plurality of solder elements of the BGA and at least a portion of respective landing pads thereof.

摘要翻译： 在一个实施例中，IC芯片封装可以包括IC芯片，其包括包括延伸超过IC芯片的侧壁的突出部分的上表面，以及围绕侧壁和突出部分的底部填充材料。 悬垂防止底部填充材料在IC芯片的上表面上延伸。 在另一个实施例中，首先将球栅阵列（BGA）安装到两个连接的IC芯片封装的较低的焊盘上。 由于BGA首先形成在下部IC芯片封装上，所以BGA用作其上的底部填充材料的坝。 底部填充材料围绕相应的IC芯片延伸并围绕BGA的多个焊料元件的底部以及其各自的着陆焊盘的至少一部分。

公开(公告)号：US07825511B2

公开(公告)日：2010-11-02

申请号：US12357484

申请日：2009-01-22

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/12

CPC分类号： H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/0501 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

摘要翻译： 一种用于在形成用于BLM（限流冶金）的C4焊料凸块并提高C4间距时消除底切的系统和方法。 在该过程中，在金属焊盘层上方沉积阻挡层金属堆叠。 通过CMP对阻挡层金属（例如Cu）的顶层进行图案化，通过蚀刻去除阻挡金属叠层的底部导电层。 扩散阻挡层和C4焊料凸点可以通过化学镀来形成，在一个实施例中，使用无掩模技术，或通过使用图案化掩模的电镀技术形成。 这样可以减少C4焊料凸点的间距。