公开(公告)号：US10559551B2

公开(公告)日：2020-02-11

申请号：US16377034

申请日：2019-04-05

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L23/538 ,  H01L23/40 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US20190229096A1

公开(公告)日：2019-07-25

申请号：US16377034

申请日：2019-04-05

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L23/40 ,  H01L23/367 ,  H01L23/373

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US09768149B2

公开(公告)日：2017-09-19

申请号：US14716176

申请日：2015-05-19

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC: H01L23/373 ,  H01L23/34 ,  H01L25/065 ,  H01L21/50 ,  H01L25/00 ,  H01L21/78 ,  H01L23/40 ,  H01L23/367 ,  H01L23/00 ,  H01L25/18 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/3738 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2224/83

Abstract: Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

公开(公告)号：US20170222111A1

公开(公告)日：2017-08-03

申请号：US15490859

申请日：2017-04-18

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar

IPC: H01L33/62 ,  H01L33/58 ,  H01L33/48 ,  H01L33/50 ,  H01L33/54

CPC classification number: H01L33/62 ,  H01L31/0203 ,  H01L31/02322 ,  H01L31/18 ,  H01L33/486 ,  H01L33/505 ,  H01L33/507 ,  H01L33/508 ,  H01L33/54 ,  H01L33/58 ,  H01L2224/73204 ,  H01L2933/0033 ,  H01L2933/0041 ,  H01L2933/005 ,  H01L2933/0058 ,  H01L2933/0066 ,  Y02E10/52

Abstract: Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device includes a radiation transducer (e.g., a light-emitting diode) and a transmissive support assembly including a transmissive support member, such as a transmissive support member including a converter material. A lead can be positioned at a back side of the transmissive support member. The radiation transducer can be flip-chip mounted to the transmissive support assembly. For example, a solder connection can be present between a contact of the radiation transducer and the lead of the transmissive support assembly.

公开(公告)号：US20160372452A1

公开(公告)日：2016-12-22

申请号：US15254586

申请日：2016-09-01

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/36 ,  H01L23/3675 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

公开(公告)号：US20160013114A1

公开(公告)日：2016-01-14

申请号：US14330900

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L23/34 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/4275 ,  H01L23/473 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，电气安装到封装支撑衬底的第一半导体管芯和多个第二半导体管芯。 第一模具具有堆叠位置和从堆叠位置​​横向延伸的周边区域，并且底部第二半导体管芯附接到第一管芯的堆叠位置。 组件还包括（a）附接到第一模具的周边区域的热转印结构，其具有第二模具所在的空腔和入口，以及（b）空腔中的底部填充材料。 底部填充材料在第二半导体管芯之间具有由底部填充材料通过壳体的入口注入空腔而引起的圆角。

公开(公告)号：US20230395463A1

公开(公告)日：2023-12-07

申请号：US18454703

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/373 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L23/44 ,  H01L25/50 ,  H01L21/563 ,  H01L24/83 ,  H01L23/3675 ,  H01L25/18 ,  H01L23/04 ,  H01L21/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/92 ,  H01L25/0657 ,  H01L23/3736 ,  H01L24/73 ,  H01L21/52 ,  H01L21/54 ,  H01L23/053 ,  H01L23/3128 ,  H01L2924/156 ,  H01L2924/1815 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/17519 ,  H01L2224/2939 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2224/83104 ,  H01L2224/1329

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US11735549B2

公开(公告)日：2023-08-22

申请号：US17376934

申请日：2021-07-15

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1146 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14517 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

公开(公告)号：US11631630B2

公开(公告)日：2023-04-18

申请号：US17175006

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

公开(公告)号：US10784224B2

公开(公告)日：2020-09-22

申请号：US16541449

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Kyle K. Kirby ,  Owen R. Fay ,  Sameer S. Vadhavkar

IPC: H01L23/00 ,  H01L23/24 ,  H01L21/56 ,  H01L23/31

Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.