公开(公告)号：US09786643B2

公开(公告)日：2017-10-10

申请号：US14325619

申请日：2014-07-08

Applicant: Micron Technology, Inc.

Inventor： Zhaohui Ma ,  Wei Zhou ,  Chee Chung So ,  Soo Loo Ang ,  Aibin Yu

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/81 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A protective material may be positioned between the die stacks and in the trenches, after which the wafer is thinned from a side opposite the die stacks to expose the protective material in the trenches. Semiconductor devices comprising stacks of dice and corresponding base semiconductor dice comprising wafer regions are separated from one another by cutting through the protective material along the streets and in the trenches. The protective material covers at least sides of each die stack as well as side surfaces of the corresponding base semiconductor die.

公开(公告)号：US09786612B2

公开(公告)日：2017-10-10

申请号：US15446583

申请日：2017-03-01

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

公开(公告)号：US09716019B2

公开(公告)日：2017-07-25

申请号：US15134788

申请日：2016-04-21

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Zhaohui Ma ,  Aibin Yu

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/373 ,  H01L25/065 ,  H01L25/00 ,  H01L23/433 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/367 ,  H01L21/78

CPC classification number: H01L21/4882 ,  H01L21/4878 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/4334 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/29191 ,  H01L2224/293 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/15787

Abstract: Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies. A heat sink is disposed on the stack of semiconductor dies and adjacent the mold material. The heat sink includes an exposed surface and a plurality of heat transfer features along the exposed surface that are configured to increase an exposed surface area compared to a planar surface.

公开(公告)号：US09589933B2

公开(公告)日：2017-03-07

申请号：US14312147

申请日：2014-06-23

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

IPC: H01L21/78 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

Abstract translation: 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。 制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。 模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。 可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。 然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

公开(公告)号：US09337064B2

公开(公告)日：2016-05-10

申请号：US14485973

申请日：2014-09-15

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Aibin Yu ,  Zhaohui Ma

IPC: H01L23/495 ,  H01L23/58 ,  H01L21/00 ,  H01L21/56 ,  H01L21/311 ,  H01L21/306 ,  H01L21/324 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. Processing systems and in-process semiconductor wafers are also disclosed.

Abstract translation: 处理半导体晶片的方法可以包括例如封装半导体材料晶片的活性表面和每个侧表面，位于晶片的有效表面上的多个半导体器件，位于 晶片的背面表面和载体基板的侧表面的至少一部分通过胶粘材料固定在晶片上。 粘合剂材料的侧表面的至少一部分可以通过去除包封材料的至少一部分而暴露。 载体衬底可以从晶片分离。 还公开了处理系统和工艺中半导体晶片。

公开(公告)号：US20150371969A1

公开(公告)日：2015-12-24

申请号：US14312147

申请日：2014-06-23

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma ,  Bret K. Street

IPC: H01L25/065 ,  H01L21/77

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in streets and at least surrounding stacks of semiconductor dice located on a wafer. Wafer-level methods of preparing semiconductor devices may involve attaching a wafer to a carrier substrate and forming stacks of laterally spaced semiconductor dice on die locations of the wafer. Molding material may be disposed over the die stacks on a surface of the wafer to at least surround the stacks of semiconductor dice with the molding material. Grooves may be formed in the molding material by partially cutting through the molding material between at least some of the stacks of semiconductor dice along streets between the die stacks. The resulting wafer-level assembly may then, when exposed to elevated temperatures during, for example, debonding the wafer from a carrier, exhibit reduced propensity for warping.

Abstract translation: 处理半导体器件的晶片级方法可以包括部分地通过模制材料形成凹槽，模制材料位于街道上，并且至少围绕位于晶片上的半导体芯片堆叠。 制备半导体器件的晶片级方法可以包括将晶片附着到载体衬底并且在晶片的芯片位置上形成横向间隔开的半导体晶片的堆叠。 模制材料可以设置在晶片的表面上的模具堆叠上，以至少用模制材料围绕半导体晶片的堆叠。 可以通过在模具堆叠之间沿着街道的半导体芯片的至少一些堆叠之间部分地切割模制材料，而在模制材料中形成凹槽。 然后，当例如在晶片脱离载体时暴露于升高的温度时，所得到的晶片级组件可能表现出降低的翘曲倾向。

公开(公告)号：US20140141544A1

公开(公告)日：2014-05-22

申请号：US14166490

申请日：2014-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Meow Koon Eng ,  Sui Waf Low ,  Min Yu Chan ,  Yong Poo Chia ,  Bok Leng Ser ,  Wei Zhou

IPC: H01L21/48 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L21/4842 ,  H01L22/10 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract translation: 微电子部件封装包括耦合到微电子部件并且具有向外延伸超过密封剂的外围边缘的暴露长度的多个电引线。 多个端子可以位于密封剂的端面附近，并且这些端子可以电耦合到相同的引线。 这可以有助于使用引线作为常规引线封装将微电子部件连接到基板。 然而，这些端子可以促进引线封装与一个或多个额外的微电子部件例如BGA封装的堆叠。

公开(公告)号：US12300570B2

公开(公告)日：2025-05-13

申请号：US17583038

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Kyle K. Kirby

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/603 ,  H01L23/31 ,  H01L23/544 ,  H01L25/16

Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

公开(公告)号：US12087719B2

公开(公告)日：2024-09-10

申请号：US17174827

申请日：2021-02-12

Applicant: Micron Technology, Inc.

Inventor： Aibin Yu ,  Wei Zhou ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/05078 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/1701 ,  H01L2224/80051 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/01029 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/03616 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/05572 ,  H01L2924/00012

Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

公开(公告)号：US12074094B2

公开(公告)日：2024-08-27

申请号：US17670378

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/8319 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.