公开(公告)号：US4813129A

公开(公告)日：1989-03-21

申请号：US64411

申请日：1987-06-19

申请人： Marcos Karnezos

发明人： Marcos Karnezos

IPC分类号： H05K3/36 ,  H01L21/60 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01R12/71 ,  H01R13/24 ,  H05K1/11 ,  H05K1/14 ,  H05K3/06 ,  H05K3/32 ,  H05K3/40 ,  H01R9/09

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/81 ,  H01R12/714 ,  H01R13/2464 ,  H05K3/325 ,  H05K3/4007 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/113 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09745 ,  H05K2201/09909 ,  H05K2201/10719 ,  Y10T29/4913

摘要： An interconnect structure for electrically coupling conductive paths on two adjacent, rigid substrates, such as PC boards or IC chips. The interconnect structure includes a number of buttons formed on a first substrate, and a number of contacts formed on a second substrate. The buttons are elastically deformable, and include a resilient core made from an organic material such as polyimide, and a metallic coating formed over the core. The two substrates are compressed between mounting plates such that the buttons are pressed against the contracts to make electrical contact.

公开(公告)号：US08410596B2

公开(公告)日：2013-04-02

申请号：US12059077

申请日：2008-03-31

申请人： Marcos Karnezos

发明人： Marcos Karnezos

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die and with other elements. Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the land side of the metal layer.

摘要翻译： 单个金属层带基板包括固定到图案化电介质层上的图案化金属层。 对电介质层进行图案化以提供在金属层的接地侧上的接合指状物上的接合区和接合位置的开口。 金属层被图案化以提供适合于与管芯和其它元件的互连的电路迹线。 通过引线接合到金属层的管芯附着侧上的暴露的迹线，并且在金属层的陆侧上设置用于接触测试封装的接合指状物和焊盘来进行与管芯的互连。

公开(公告)号：US07687313B2

公开(公告)日：2010-03-30

申请号：US12042312

申请日：2008-03-04

申请人： Marcos Karnezos

发明人： Marcos Karnezos

IPC分类号： H01L21/48 ,  B23K31/02

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/056 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2224/16225 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

摘要： A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 提供一种制造半导体多封装模块的方法，通过提供包括下基板和模具的下模制球栅阵列封装，将包括反向取向的上基板的上模制封装固定到下封装的上表面上 并且在上基板和下基板之间形成z-互连。

公开(公告)号：US07429787B2

公开(公告)日：2008-09-30

申请号：US11397027

申请日：2006-03-31

申请人： Marcos Karnezos ,  IL Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna ,  Seng Guan Chow

发明人： Marcos Karnezos ,  IL Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna ,  Seng Guan Chow

IPC分类号： H01L23/02 ,  H01L21/00 ,  H05K1/14

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49833 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated with both the land side of the second substrate and a portion of the land side of the first package substrate exposed, so that second level interconnection and interconnection with additional components may be made.

摘要翻译： 半导体组件包括：第一封装，每个封装具有至少一个管芯，其固定到第一封装衬底的管芯附着侧并与之电互连，以及具有第一侧面和第二（“焊盘”）侧的第二衬底， 在第一封装的模制中，第二衬底的第一面面向第一封装衬底的裸片附着侧。 封装和基板的Z形互连是通过连接第一和第二基板的引线键合。 组件被封装在第二衬底的接地侧和第一封装衬底的接地侧的一部分之间，从而可以形成第二级互连和与附加部件的互连。

公开(公告)号：US07429786B2

公开(公告)日：2008-09-30

申请号：US11394635

申请日：2006-03-31

申请人： Marcos Karnezos ,  Flynn Carson

发明人： Marcos Karnezos ,  Flynn Carson

IPC分类号： H01L23/02 ,  H05K1/18

CPC分类号： H01L25/0657 ,  H01L23/552 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package subassembly includes a die affixed to, and electrically interconnected with, a die attach side of a first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the first package with the first side of the second substrate facing the die attach side of the first package substrate, and supported by a spacer or a spacer assembly. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made.

摘要翻译： 半导体封装子组件包括固定到第一封装衬底的管芯附接侧并与之电互连的管芯，以及具有安装在第一封装上的第一侧和第二（“焊盘”）侧的第二衬底， 第二基板的第一面朝向第一封装基板的管芯附接侧，并由间隔件或间隔件组件支撑。 封装和基板的Z形互连是通过连接第一和第二基板的引线键合。 该组件以这样一种方式封装，使得第二基板的接地侧（组件的一侧）和第一封装基板的陆部侧的一部分（在组件的相对侧）被露出，使得 可以进行二级互连和与附加组件的互连。

公开(公告)号：US07364946B2

公开(公告)日：2008-04-29

申请号：US11626272

申请日：2007-01-23

申请人： Marcos Karnezos

发明人： Marcos Karnezos

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/056 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2224/16225 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

摘要： A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 提供一种制造半导体多封装模块的方法，通过提供包括下基板和模具的下模制球栅阵列封装，将包括反向取向的上基板的上模制封装固定到下封装的上表面上 并且在上基板和下基板之间形成z-互连。

公开(公告)号：US07358115B2

公开(公告)日：2008-04-15

申请号：US11626232

申请日：2007-01-23

申请人： Marcos Karnezos

发明人： Marcos Karnezos

IPC分类号： H01L21/48 ,  H01L23/02 ,  B23K31/02 ,  H01K1/14

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 半导体多封装模块具有堆叠的下封装和上封装，每个封装包括附接到基板的管芯，其中上基板和下基板通过引线接合互连，并且其中上封装反向。 另外，制造半导体多封装模块的方法通过提供包括下基板和模具的下模制封装，将包括反向取向的上基板的上模制封装固定在下封装的上表面上，以及形成 在上和下基板之间的z-互连。

公开(公告)号：US20070278658A1

公开(公告)日：2007-12-06

申请号：US11772776

申请日：2007-07-02

申请人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

发明人： Marcos Karnezos ,  Flynn Carson ,  Youngcheol Kim

IPC分类号： H01L23/12 ,  H01L21/58 ,  H01L23/48

CPC分类号： H01L25/03 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multipackage module has multiple die of various types and having various functions and, in some embodiments, the module includes a digital processor, an analog device, and memory. A first die, having a comparatively large footprint, is mounted onto first die attach region on a surface of a first package substrate. A second die, having a significantly smaller footprint, is mounted upon the surface of the first die, on a second die attach region toward one edge of the first die. The first die is electrically connected by wire bonds to conductive traces in the die-attach side of the substrate. The second die is electrically connected by wire bonds to the first package substrate, and may additionally be electrically connected by wire bonds to the first die. In some embodiments a spacer is mounted upon the first die, on a spacer attach region of the surface of the first die that is not within the die attach region, and which may be generally near a margin of the first die. A land grid array (LGA) package is inverted and mounted upon the spacer, with one margin of the LGA package near the edge of the spacer, so that much of the LGA package overhangs the second die. In other embodiments an additional spacer is mounted upon the first die, on a second spacer attach region that is not within the die attach region and not within the first spacer attach region, and the inverted LGA package is mounted upon both spacers. In still other embodiments a first spacer having a thickness approximating the thickness of the second die is mounted in a spacer attach region upon the first die; additional spacers are mounted upon both the first spacer and the second die, and the inverted LGA package is mounted upon the additional spacers. The LGA package is electrically connected to the first package substrate by wire bonds between bond sites on the LGA package and bond sites on the BGA package.

公开(公告)号：US07279361B2

公开(公告)日：2007-10-09

申请号：US11374468

申请日：2006-03-13

申请人： Marcos Karnezos

发明人： Marcos Karnezos

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49833 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 一种半导体多封装模块，其具有堆叠的下封装和上封装，每个封装包括附接到基板的管芯，其中上基板和下基板通过引线接合互连。 另外，制造半导体多封装模块的方法是通过提供包括下部基板和模具的下部模制封装，将包括上部基板的上部模制封装固定到下部封装的上表面上，并且形成z-互连 在上下基板之间。

公开(公告)号：US07247519B2

公开(公告)日：2007-07-24

申请号：US11337944

申请日：2006-01-23

申请人： Marcos Karnezos ,  Flynn Carson

发明人： Marcos Karnezos ,  Flynn Carson

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L25/03 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/056 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/0665 ,  H01L2224/16225 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

摘要： A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

摘要翻译： 半导体多封装模块具有堆叠的下封装和上封装，每个封装包括附接到基板的管芯，其中第二封装反相，其中上基板和下基板通过引线接合互连，并且其中倒置 第二封装包括凸块芯片载体封装。 另外，制造半导体多封装模块的方法通过提供包括下基板和芯片的下模塑封装，将包括反向取向的上基板的上凸块芯片载体封装固定在下封装的上表面上， 以及在上基板和下基板之间形成z-互连。